Motorola MC68HC05T16 Technical Data Manual Download

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MOTOROLA
11-10

MC68HC05L1

CPU CORE AND INSTRUCTION SET

Table 11-8 M68HC05 opcode map

Bit manipulation

Branc

Read/modify/write

Contr

Register/memor

BTB

BSC

REL

DIR

INH

IX1

INH

IMM

DIR

EXT

IX2

IX1

High

0123456789

High

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

0000

553533659

234543

0000

BRSET0

BSET0

BRA

NEG

NEGA

NEGX

NEG

SUB

BTB

BSC

REL

DIR

INH

IX1

INH

IMM

DIR

EXT

IX2

IX1

0001

553

234543

0001

BRCLR0

BCLR0

BRN

CMP

BTB

BSC

REL

INH

IMM

DIR

EXT

IX2

IX1

0010

553

234543

0010

BRSET1

BSET1

BHI

MUL

SBC

BTB

BSC

REL

INH

IMM

DIR

EXT

IX2

IX1

0011

55353365

234543

0011

BRCLR1

BCLR1

BLS

COM

COMA

COMX

COM

SWI

CPX

BTB

BSC

REL

DIR

INH

IX1

INH

IMM

DIR

EXT

IX2

IX1

0100

55353365

234543

0100

BRSET2

BSET2

BCC

LSR

LSRA

LSRX

LSR

AND

BTB

BSC

REL

DIR

INH

IX1

IMM

DIR

EXT

IX2

IX1

0101

553

234543

0101

BRCLR2

BCLR2

BCS

BIT

BTB

BSC

REL

IMM

DIR

EXT

IX2

IX1

0110

55353365

234543

0110

BRSET3

BSET3

BNE

ORA

ORX

BTB

BSC

REL

DIR

INH

IX1

IMM

DIR

EXT

IX2

IX1

0111

55353365

45654

0111

BRCLR3

BCLR3

BEQ

ASR

ASRA

ASRX

ASR

BTB

BSC

REL

DIR

INH

IX1

INH

DIR

EXT

IX2

IX1

1000

55353365

2234543

1000

BRSET4

BSET4

BHCC

LSL

LSLA

LSLX

LSL

CLC

EOR

BTB

BSC

REL

DIR

INH

IX1

INH

IMM

DIR

EXT

IX2

IX1

1001

55353365

2234543

1001

BRCLR4

BCLR4

BHCS

OLA

OLX

SEC

ADC

BTB

BSC

REL

DIR

INH

IX1

INH

IMM

DIR

EXT

IX2

IX1

1010

55353365

2234543

1010

BRSET5

BSET5

BPL

DEC

DECA

DECX

DEC

CLI

ORA

BTB

BSC

REL

DIR

INH

IX1

INH

IMM

DIR

EXT

IX2

IX1

1011

553

2234543

1011

BRCLR5

BCLR5

BMI

SEI

ADD

BTB

BSC

REL

INH

IMM

DIR

EXT

IX2

IX1

1100

55353365

23432

1100

BRSET6

BSET6

BMC

INC

INCA

INCX

INC

RSP

JMP

BTB

BSC

REL

DIR

INH

IX1

INH

DIR

EXT

IX2

IX1

1101

55343354

2656765

1101

BRCLR6

BCLR6

BMS

TST

TSTX

TST

NOP

BSR

JSR

BTB

BSC

REL

DIR

INH

IX1

INH

REL

DIR

EXT

IX2

IX1

1110

553

234543

1110

BRSET7

BSET7

BIL

LDX

BTB

BSC

REL

INH

IMM

DIR

EXT

IX2

IX1

1111

5535336522

45654

1111

BRCLR7

BCLR7

BIH

CLR

CLRA

CLRX

CLR

AIT

TXA

STX

BTB

BSC

REL

DIR

INH

IX1

INH

DIR

EXT

IX2

IX1

1111

0000

SUB

Opcode in he

xadecimal

Opcode in binar

Address mode

Cycles

Bytes

Mnemonic

Leg

end

Abbre

viations f

or ad

dress modes and register

BSC

BTB

DIR

EXT

INH

IMM

IX1

IX2

REL

Bit set/clear

Bit test and br

anch

Direct

Extended

Inherent

Immediate

Inde

xed (no offset)

Inde

xed, 1 b

yte (8-bit) offset

Inde

xed, 2 b

yte (16-bit) offset

Relativ

Accum

ulator

Inde

x register

Not implemented

TPG

100

Summary of Contents for MC68HC05T16

Page 1: ...HC05 MC68HC05T16D H MC68HC05T16 MC68HC705T16 TECHNICAL DATA MOTOROLA MC68HC05T16 MOTOROLA TECHNICAL DATA ...

Page 2: ......

Page 3: ...UT OUTPUT PORTS MEMORY AND REGISTERS RESETS AND INTERRUPTS TIMERS M BUS SERIAL INTERFACE PULSE ACCUMULATOR PULSE WIDTH MODULATOR ON SCREEN DISPLAY ANALOG TO DIGITAL CONVERTER CPU CORE AND INSTRUCTION SET LOW POWER MODES OPERATING MODES ELECTRICAL SPECIFICATIONS MECHANICAL SPECIFICATIONS ...

Page 4: ...PUT PORTS MEMORY AND REGISTERS RESETS AND INTERRUPTS TIMERS M BUS SERIAL INTERFACE PULSE ACCUMULATOR PULSE WIDTH MODULATOR ON SCREEN DISPLAY ANALOG TO DIGITAL CONVERTER CPU CORE AND INSTRUCTION SET LOW POWER MODES OPERATING MODES ELECTRICAL SPECIFICATIONS MECHANICAL SPECIFICATIONS TPG 2 ...

Page 5: ...o support or sustain life or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries affiliates and distributors harmless against all claims...

Page 6: ...verbar is used to designate an active low signal eg RESET Unless otherwise stated blank cells in a register diagram indicate that the bit is either unused or reserved shaded cells indicate that the bit is not described in the following paragraphs u is used to indicate an undefined state on reset ...

Page 7: ...the task s outlined in question 2 Completely Not at all Comments 4 How easy is it to find the information you are looking for Easy Difficult Comments 5 Is the level of technical detail in the following sections sufficient to allow you to understand how the device functions Too little detail Too much detail Comments 6 Have you found any errors If so please comment 7 From your point of view is anyth...

Page 8: ...is document 9 How would you rate Motorola s documentation Excellent Poor In general Against other semiconductor suppliers 10 Which semiconductor manufacturer provides the best technical documentation 11 Which company in any field provides the best technical documentation 12 How many years have you worked with microprocessors Less than 1 year 1 3 years 3 5 years More than 5 years By air mail Par av...

Page 9: ...t Programming 2 4 2 2 2 Port E and F Configuration Registers 2 4 3 MEMORY AND REGISTERS 3 1 Memory Map 3 1 3 2 Input Output Section 3 1 3 3 RAM 3 1 4 RESETS AND INTERRUPTS 4 1 RESETS 4 1 4 1 1 Power On Reset POR 4 1 4 1 2 RESET Pin 4 1 4 1 3 Computer Operating Properly COP Reset 4 2 4 2 INTERRUPTS 4 4 4 2 1 Hardware Controlled Sequences 4 5 4 2 2 Software Interrupt SWI 4 6 4 2 3 External Interrupt...

Page 10: ...5 2 1 COP Watchdog Reset 5 11 6 M BUS SERIAL INTERFACE 6 1 M Bus Interface Features 6 1 6 2 M Bus Protocol 6 2 6 2 1 START Signal 6 3 6 2 2 Slave Address Transmission 6 3 6 2 3 Data Transfer 6 4 6 2 4 Repeated START Signal 6 4 6 2 5 STOP Signal 6 4 6 2 6 Arbitration Procedure 6 4 6 2 7 Clock Synchronization 6 5 6 2 8 Handshaking 6 5 6 3 M Bus Registers 6 5 6 3 1 M Bus Address Register MADR 6 6 6 3...

Page 11: ...9 4 Row 9 7 9 4 1 Row Attribute Register 9 7 9 4 2 Row Vertical Position Registers 9 8 9 4 3 Row Horizontal Position Register 9 12 9 4 4 Row Control Register 1 9 12 9 4 5 Row Control Register 2 9 13 9 5 Frame 9 13 9 5 1 Frame Control 1 and Row Count Register 9 14 9 5 2 Frame Control Register 2 9 15 9 5 3 Frame Control 3 and Status Register 9 17 10 ANALOG TO DIGITAL CONVERTER 10 1 ADC Inputs 10 2 1...

Page 12: ... 11 3 2 Immediate 11 11 11 3 3 Direct 11 11 11 3 4 Extended 11 12 11 3 5 Indexed no offset 11 12 11 3 6 Indexed 8 bit offset 11 12 11 3 7 Indexed 16 bit offset 11 12 11 3 8 Relative 11 13 11 3 9 Bit set clear 11 13 11 3 10 Bit test and branch 11 13 12 LOW POWER MODES 12 1 Stop Mode 12 1 12 1 1 Timer during Stop Mode 12 1 12 1 2 M Bus during Stop Mode 12 2 12 1 3 Pulse Accumulator during Stop Mode ...

Page 13: ... 5 14 ELECTRICAL SPECIFICATIONS 14 1 Maximum Ratings 14 1 14 2 Thermal Characteristics 14 1 14 3 DC Electrical Characteristics 14 2 14 4 Open Drain Electrical Specification 14 3 14 5 On Screen Display Timing 14 3 14 6 M Bus Interface Timing 14 4 14 7 Control Timing 14 5 15 MECHANICAL SPECIFICATIONS 15 1 56 pin SDIP Package 15 1 TPG 11 ...

Page 14: ...MOTOROLA vi MC68HC05T16 THIS PAGE LEFT BLANK INTENTIONALLY TPG 12 ...

Page 15: ... Diagram for Timer Overflow 5 9 6 1 M Bus Interface Block Diagram 6 2 6 2 M Bus Transmission Signal Diagram 6 3 6 3 Clock Synchronization 6 5 8 1 7 Bit PWM Output Waveform 8 2 8 2 14 Bit PWM Output Waveform 8 3 9 1 OSD Character and Row Structure 9 4 9 2 Reserved Character ROM Codes 9 5 9 3 Color Palette Organization 9 6 9 4 Output Signal Timing Diagram Without Background 9 10 9 5 Output Signal Ti...

Page 16: ...MOTOROLA viii MC68HC05T16 THIS PAGE LEFT BLANK INTENTIONALLY TPG 14 ...

Page 17: ...ion 11 5 11 2 Register memory instructions 11 5 11 3 Branch instructions 11 6 11 4 Bit manipulation instructions 11 6 11 5 Read modify write instructions 11 7 11 6 Control instructions 11 7 11 7 Instruction set 11 8 11 8 M68HC05 opcode map 11 10 13 1 Mode Selection 13 2 13 2 Self Check Report 13 4 14 1 DC Electrical Characteristics for 5V Operation 14 2 14 2 Open Drain Parameters 14 3 14 3 On Scre...

Page 18: ...MOTOROLA x MC68HC05T16 THIS PAGE LEFT BLANK INTENTIONALLY TPG 16 ...

Page 19: ...the text 1 1 Features 8 bit architecture Power saving Stop Wait modes 320 bytes of on chip RAM 64 bytes for stack 24064 bytes of on chip ROM EPROM PLL based 4 row buffer On Screen Display OSD 128 character 4K bytes OSD ROM EPROM 16 character 512 bytes dual ported OSD RAM both readable and writable by CPU 40 bidirectional I O lines 24 dedicated and 16 multiplexed I O lines 12 of the 24 dedicated I ...

Page 20: ... 4 5 0 0 0 0 0 1 1 1 1 1 H I N Z C COP SYSTEM OSC POWER EXTAL XTAL VDD VSS DDR A PORT A PA0 PA7 DDR E PORT E PE0 PWM0 PE1 PWM1 PE2 PWM2 PE3 PWM3 PE4 PWM4 PE5 PWM5 PE6 PWM6 PE7 PWM7 8 2 OSD PLL VCO RP HFLBK R G B FBKG VFLBK OSD CHAR ROM OSD CHAR RAM OSD MULTI FUNCTION TIMER 16 BIT TIMER DDR B PORT B PB0 PB7 8 DDR C PORT C PC0 PC3 4 PC4 PC7 4 DDR F PORT F PF0 PWM8 PF1 PWM9 PF2 I PF3 HTONE PF4 ADCIN1...

Page 21: ...705T16 this is the EPROM programming voltage input pin RESET 53 The active low RESET input is not required for start up but can be used to reset the MCU internal state and provide an orderly software start up procedure TCAP 15 The TCAP input controls the input capture feature for the on chip programmable free running timer EXTAL XTAL 51 52 These pins provide connections to the on chip oscillator T...

Page 22: ...r creating transparent background effect when the background of a character window overlaps the original TV picture display These pins are shared with port pins PF2 and PF3 Selection is by the port F Configuration register 0D bits 2 and 3 respectively ADCIN0 ADCIN1 14 10 These are the two input channels to the analog to digital converter ADCIN1 pin is shared with port PF4 and is selected by settin...

Page 23: ...33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 PE3 PWM3 PE4 PWM4 PE5 PWM5 PE6 PWM6 PE7 PWM7 PF0 PWM8 PF1 PWM9 PF2 I PF3 HTONE PF4 ADCIN1 PF5 SDA PF6 SCL PF7 PACIN ADCIN0 TCAP PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PA7 PA6 PA5 PA4 PA3 PE2 PWM2 PE1 PWM1 PE0 PWM0 RESET XTAL EXTAL R G B FBKG VFLBK HFLBK VSS VCO RP VDD PC0 PC1 IRQ VPP PC2 PC3 PC4 PC5 PC6 PC7 PA0 PA1 PA2 32 30 29...

Page 24: ...data latch and not the I O pin 2 2 2 Port E and F Configuration Registers Port E and F are shared with PWM PAC OSD MBUS and ADC The configuration registers at 0C and 0D are used to configure these I O pins The default state after a reset or POR is zero Setting the corresponding bits will enable the corresponding functions For example setting the SDA and SCL bits will configure PF5 and PF6 as MBUS ...

Page 25: ...TION REGISTER BIT LATCHED OUTPUT DATA BIT INTERNAL MC68HC05 CONNECTIONS DDR 7 DDR 6 DDR 5 DDR 4 DDR 3 DDR 2 DDR 1 DDR 0 0 1 2 3 4 5 6 7 Px7 Px6 Px5 Px4 Px3 Px2 Px1 Px0 TYPICAL PORT DATA DIRECTION REGISTER TYPICAL PORT REGISTER I O PORT LINES VDD PAD IP PORT DATA PORT DDR INTERNAL LOGIC P N NOTE 1 IP INPUT PROTECTION 2 LATCH UP PROTECTION NOT SHOWN a b c TPG 23 ...

Page 26: ...MOTOROLA 2 6 MC68HC05T16 PIN DESCRIPTIONS AND INPUT OUTPUT PORTS 2 THIS PAGE LEFT BLANK INTENTIONALLY TPG 24 ...

Page 27: ...ry space 0000 003F are the I O section These are the addresses of the I O control registers status registers and data registers Table 3 1 shows these registers and their respective bits 3 3 RAM The 320 addresses from 0050 018F are RAM locations The CPU uses the 64 RAM addresses 00C0 00FF as the stack Before processing an interrupt the CPU uses five bytes of the stack to save the contents of the CP...

Page 28: ...ntal Position Register OSD Row Control 1 Register OSD Row Control 2 Register OSD Frame Control 3 and Status Register PWM0 Register PWM1 Register PWM2 Register PWM3 Register PWM5 Register PWM7 Register PWM8 Register PWM9L Register PWM9H Register M Bus Address Register M Bus Clock Register M Bus Status Register M Bus Data Register ADC Control and Status Register ERPOM Programming Control Register Re...

Page 29: ...a PAD7 PAD6 PAD5 PAD4 PAD3 PAD2 PAD1 PAD0 10 Timer control ICIE OC0IE OC1IE TOVFIE IEDG 11 Timer status ICF OC0F OC1F TOF TCAPS 12 Timer input capture high CAP7H CAP6H CAP5H CAP4H CAP3H CAP2H CAP1H CAP0H 13 Timer input capture low CAP7L CAP6L CAP5L CAP4L CAP3L CAP2L CAP1L CAP0L 14 Timer output compare 0 high 0CMP7H 0CMP6H 0CMP5H 0CMP4H 0CMP3H 0CMP2H 0CMP1H 0CMP0H 15 Timer output compare 0 low 0CMP...

Page 30: ...VFLB R3CF R2CF R1CF R0CF 2C PWM0 0PWM6 0PWM5 0PWM4 0PWM3 0PWM2 0PWM1 0PWM0 2D PWM1 1PWM6 1PWM5 1PWM4 1PWM3 1PWM2 1PWM1 1PWM0 2E PWM2 2PWM6 2PWM5 2PWM4 2PWM3 2PWM2 2PWM1 2PWM0 2F PWM3 3PWM6 3PWM5 3PWM4 3PWM3 3PWM2 3PWM1 3PWM0 30 PWM4 4PWM6 4PWM5 4PWM4 4PWM3 4PWM2 4PWM1 4PWM0 31 PWM5 5PWM6 5PWM5 5PWM4 5PWM3 5PWM2 5PWM1 5PWM0 32 PWM6 6PWM6 6PWM5 6PWM4 6PWM3 6PWM2 6PWM1 6PWM0 33 PWM7 7PWM6 7PWM5 7PWM4...

Page 31: ...e power supply voltage There is no provision for a power down reset The power on circuitry provides for a 4064 tcyc delay from the time that the oscillator becomes active If the external RESET pin is low at the end of the 4064 tcyc time out the processor remains in the reset condition until RESET goes high The user must ensure that VDD has risen to a point where the MCU can operate properly prior ...

Page 32: ... disabled by software Table 4 1 shows the internal circuit actions on reset but not necessary in order of occurrence Table 4 1 Reset Action on Internal Circuit DEFAULT CONDITIONS AFTER RESET 1 Timer prescaler reset to zero state 2 Timer counter configures to FFFC 3 All timer interrupt enable bits cleared ICIE OC0IE OC1IE and TOVFIE to disable timer interrupt 4 All data direction registers cleared ...

Page 33: ...FFFF t VDDR VDD THRESHOLD TYPICALLY 1 2V 4064 tcyc toxov tcyc 3 NEW PCH NEW PCL OP CODE tRL 1 5tCYC PCH PCL OP CODE NEW PC NOTES 1 EXTAL is not meant to represent frequency It is only used to represent time 2 Internal clock internal address bus and internal data bus signals are not available externally 3 Next rising edge of internal clock after rising edge of RESET initiates reset sequence TPG 31 ...

Page 34: ...e end of the current instruction execution The state of the machine is pushed onto the stack see Figure 4 2 for stacking order and the appropriate vector points to the starting address of the interrupt service routine see Table 4 2 Also the interrupt mask bit in the condition code register is set This masks further interrupts At the completion of the service routine the software normally contains ...

Page 35: ...IT instruction causes all processor clocks to stop but leaves the Timer and PAC clocks running This rest state of the processor can be exited by RESET an external interrupt IRQ or any of the interrupts described above There are no special wait vectors for these individual interrupts See section 12 on Low Power Modes Table 4 2 Reset Interrupt Vector Addresses Register Flag Name Interrupt CPU Interr...

Page 36: ...set This masks further interrupts until the present one is serviced The service routine address is specified by the contents of FFF8 FFF9 The interrupt logic recognizes negative edge transitions and pulses special case of negative edges on the external interrupt line Figure 4 3 shows both a block diagram and timing for the interrupt line IRQ to the processor The first method is used if pulses on t...

Page 37: ...minimum pulse width tILIH is either 125ns VDD 5V or 250ns VDD 3V The period tILIL should not be less than the number of tcyc cycles it takes to ex ecute the interrupt service routine plus 21 tcyc cycles INTERRUPT PIN tILIL Wired ORed Interrupt signals IRQ if after servicing an interrupt the external interrupt pins remain low then the next interrupt is recognized Normally used with wired OR connect...

Page 38: ... by accessing the Input Capture register least significant byte 13 All four timer interrupt flags have corresponding enable bits ICIE OC0IE OC1IE and TOIE found in the Timer Control register TCR at location 10 Reset clears all enable bits preventing an interrupt from occurring The actual processor interrupt is generated only if the interrupt mask bit of the condition code register is also cleared ...

Page 39: ...ister matches the calling address this bit is set An interrupt is generated if the MIEN bit is set Then CPU needs to check the SRW bit and set its XMT bit accordingly Writing to the M Bus Control register clears this bit ALOST Arbitration Lost This arbitration lost bit is set by hardware when the M bus master loses arbitration during a master transmission mode This bit must be cleared by software ...

Page 40: ... OSD Interrupts There are five OSD interrupt sources VFLBK bit and R0 1 2 3CF bits of OSD Status register in the OSD module VFLB bit will be set whenever the leading edge of vertical flyback pin VFLBK has been detected An interrupt will occur if the corresponding interrupt enable bit VFINTE is set Whenever each row terminates its display RiCF bit will be set and an interrupt will be generated prov...

Page 41: ...s of memory location FFF0 and FFF1 TOF Timer Overflow 1 set 8 bit ripple timer overflow has occurred 0 clear No 8 bit ripple timer overflow has occurred This bit is set when the 8 bit ripple counter overflows from FF to 00 a timer overflow interrupt will occur if TOFIE bit 5 is set TOF is cleared by writing a 0 to the bit RTIF Real Time Interrupt Flag 1 set A real time interrupt has occurred 0 cle...

Page 42: ...rupt Enable 1 set TOF interrupt is enabled 0 clear TOF interrupt is disabled RTIE Real Time Interrupt Enable 1 set Real time interrupt circuit is active 0 clear Real time interrupt circuit is inactive Refer to section 5 2 for detailed description of Multi Function Timer TPG 40 ...

Page 43: ...te of a specific timer function allows full control of that function However an access of the high byte inhibits that specific timer function until the low byte is also accessed Note The I bit in the condition code register should be set while manipulating both the high and low byte register of a specific timer function to ensure that an interrupt does not occur Twelve 8 bit registers are associat...

Page 44: ...R 2 16 BIT FREE RUNNING COUNTER COUNTER ALTERNATE REGISTER 8 BIT BUFFER INPUT CAPTURE REGISTER OUTPUT COMPARE CIRCUIT 1 OUTPUT COMPARE CIRCUIT 2 OVERFLOW DETECT CRCUIT EDGE DETECT CIRCUIT 4 ICIE OC0IE OC1IE TOVFIE IEDG ICF OC0F OC1F TOF INTERRUPT CIRCUIT INTERNAL PROCESSOR CLOCK TIMER CONTROL REGISTER EDGE INPUT TCAP TIMER STATUS REGISTER TCAPS TPG 42 ...

Page 45: ...er Alternate register does not affect TOF Therefore the counter alternate register can be read any time without risk of missing timer overflow interrupts due to a cleared TOF The free running counter is preset to FFFC during reset and is always a read only register During a power on reset the counter is also preset to FFFC and begins running after the oscillator start up delay The value in the fre...

Page 46: ...care must be taken when initializing output compare functions with software The following procedure is recommended 1 write to Output Compare register 0 and or 1 High byte to inhibit further compares 2 read the Timer Status register to initialize clearing of OC0F or and OC1F 3 write to Output Compare register 0 or and 1 Low byte to enable the output compare function 5 1 3 Input Capture Registers In...

Page 47: ... register The other bit controls which edge is significant to the input capture edge detector The Timer Control register and the free running counter are the only sections of the timer affected by reset Definition of each bit is as follows ICIE Input Capture Interrupt Enable 1 set Input Capture interrupt enabled 0 clear Input Capture interrupt disabled OC0IE Output Compare Interrupt Enable 1 set O...

Page 48: ...t ICF is cleared by reading the TSR and then the Input Capture Low register 13 OC0F Output Compare 0 Flag 1 set A valid output compare has occurred on output compare 0 register 0 clear No output compare has occurred on output compare 0 register OC0F will be set when its output compare 0 register contents match that of the free running counter an output compare interrupt will be generated if OC0IE ...

Page 49: ...ntionally cleared if 1 the timer status register is read or written when the TOF is set and 2 the LSB of the free running counter is read but not for the purpose of servicing the flag Reading the alternate counter register instead of the counter register will avoid this potential problem TCAPS Timer Capture State 1 set TCAP pin is a logic high 0 clear TCAP pin is a logic low This bit reflects the ...

Page 50: ...OR INTERNAL TIMER CLOCKS Notes RESET affects only the Counter register and Timer Control register INTERNAL PROCESSOR CLOCK T00 T01 T10 T11 COUNTER 16 BIT INTERNAL TIMER CLOCKS F123 F124 F125 F126 F127 F125 SEE NOTE INPUT EDGE INTERNAL CAPTURE LATCH INPUT CAPTURE REGISTER INPUT CAPTURE FLAG If the input edge occurs in the shaded area from one timer state T10 to the other timer state T10 the input c...

Page 51: ... compare only occurs at the timer state T01 Thus a 4 cycle difference may exist between the write to the compare register and the actual compare 2 The output compare flag is set at the timer state T11 that follows the comparison match F547 in this example LATCH Note 1 INTERNAL PROCESSOR CLOCK T00 T01 T10 T11 COUNTER 16 BIT INTERNAL TIMER CLOCKS FFFE FFFF 0000 0001 0002 Note TIMER OVERFLOW FLAG TOF...

Page 52: ...errupt rate is then divided by 8 to generate COP reset Register bit definitions TOF Timer Overflow 1 set 8 bit ripple timer overflow has occurred 0 clear No 8 bit ripple timer overflow has occurred This bit is set when the 8 bit ripple counter overflows from FF to 00 a timer overflow interrupt will occur if TOFIE bit 5 is set TOF is cleared by writing a 0 to the bit RTIF Real Time Interrupt Flag 1...

Page 53: ... of address FFF0 The COP counter has to be cleared periodically by software with a period less than COP reset rate Watchdog timer function will stop counting in Wait and Stop modes Counting continues when it wakes up from Wait mode and a 4064 cycle delay after waking up from Stop mode The watchdog counter system is controlled by the WDOG bit in the Multi Function Timer register bit 2 of address 1C...

Page 54: ...MOTOROLA 5 12 MC68HC05T16 TIMERS 5 THIS PAGE LEFT BLANK INTENTIONALLY TPG 52 ...

Page 55: ...r of devices that can be connected are limited by a maximum bus capacitance of 400pF The M Bus system is a true multi master bus including arbitration to prevent data collision if two or more masters intend to control the bus simultaneously It may be used for rapid testing and alignment of end products via external connections to an assembly line computer 6 1 M Bus Interface Features Compatible wi...

Page 56: ...illustrated in Figure 6 2 Figure 6 1 M Bus Interface Block Diagram Internal bus Frequency divider register Address comparator Address register 8 MEN MIEN MSTR XMT ACKEB MCF SELTED BBSY LOST SRW MIF RXACKB TX shift register RX shift register RX control TX control M Bus interrupt SCL control SDA control M Bus clock generator sync logic START STOP detector and arbitration START STOP generator and tim...

Page 57: ...ission The first byte of data transfer immediately following the START signal is the slave address transmitted by the master This is a seven bits long calling address followed by a R W bit The R W bit dictates the slave of the desired direction of data transfer Only the slave with matched address will respond by sending back an acknowledge bit by pulling the SDA low at the 9th clock see Figure 6 2...

Page 58: ...to terminate the communication This is used by the master to communicate with another slave or with the same slave in a different mode transmit receive mode without releasing the bus 6 2 5 STOP Signal The master can terminate the communication by generating a STOP signal to free the bus However the master may generate a START signal followed by a calling command without generating a STOP signal fi...

Page 59: ... low periods enter a high wait state during this time See Figure 6 3 When all devices concerned have counted off their low period the synchronized clock SCL line will be released and go high All of them will start counting their high periods The first device to complete its high period will again pull the SCL line low 6 2 8 Handshaking The clock synchronization mechanism can be used as a handshake...

Page 60: ... State on reset 37 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 0000 0000 Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset 38 MBC4 MBC3 MBC2 MBC1 MBC0 0000 0000 Table 6 1 M Bus Prescaler MBC4 MBC3 MBC2 MBC1 MBC0 DIVIDER MBC4 MBC3 MBC2 MBC1 MBC0 DIVIDER 0 0 0 0 0 22 1 0 0 0 0 352 0 0 0 0 1 24 1 0 0 0 1 384 0 0 0 1 0 28 1 0 0 1 0 448 0 0 0 1 1 34 1 0 0 1 1 544 0 0 1 0 0 44 1 0 1 0 0 704 ...

Page 61: ...s selected When this bit is changed from 1 to 0 a STOP signal is generated and the operation mode changes from master to slave In master mode a bit clear immediately followed by a bit set of this bit generates a repeated START signal without generating a STOP signal XMT Transmit Receive Mode Select Bit 1 set M Bus is set for transmit mode 0 clear M Bus is set for receive mode ACKEB Acknowledge Ena...

Page 62: ... M bus interrupt bit is also set An interrupt is generated if the MIEN bit is set Then CPU needs to check the SRW bit and set its XMT bit accordingly Writing to the M Bus Control register clears this bit BBSY Bus Busy Bit 1 set M Bus busy 0 clear M Bus idle This bit indicates the status of the bus When a START signal is detected BBSY is set If a STOP signal is detected it is cleared ALOST Arbitrat...

Page 63: ... its own specific address in slave receive mode SELTED set 3 A loss of bus arbitration ALOST set This bit must be cleared by software in the interrupt routine RXACKB Receive Acknowledge Bit 1 set No acknowledgment signal detected 0 clear Acknowledgment signal detected after 8 bits data transmitted If cleared it indicates an acknowledge signal has been received after the completion of 8 bits data t...

Page 64: ...MOTOROLA 6 10 MC68HC05T16 M BUS SERIAL INTERFACE 6 THIS PAGE LEFT BLANK INTENTIONALLY TPG 62 ...

Page 65: ...t counter is driven by E clock divided by 64 The counter will increment when PACIN pin is high and halt when PACIN is low 7 1 Pulse Accumulator Registers Two registers are associated with the Pulse Accumulator they are described below 7 1 1 PAC Control and Status Register PACTL Register bit definitions PAOF PAC Overflow Interrupt Flag Bit 1 set A PAC overflow from FF to 00 has occurred 0 clear No ...

Page 66: ...t PAC overflow Interrupt enabled 0 clear PAC overflow Interrupt disabled This PAIE bit enables interrupt caused by the PAOF bit 7 1 2 PAC Counter Register When PAC is disabled PAEN 0 the counter will be cleared to zero This ensures the Counter starts from zero every time it is disabled and enabled The Pulse Accumulator Counter is read only and resets to zero a write operation Address bit 7 bit 6 b...

Page 67: ...28 x 1 262500Hz 487 62µs i e a repetition frequency of 2050 8Hz The duty cycle is proportional to the value in the corresponding PWM data register A value of 00 loaded into these registers results in a continuously low output on the corresponding PWM output pin with external pull up resistor connected A value of 40 results in a 50 duty cycle output The maximum value of 7F results in a 127 128 duty...

Page 68: ...configuring its own waveform the final PWM output waveform is a combination of the two waveforms waveforms are ORed The driving clock for the 14 bit PWM channels is CPU clock The 8 bit register works in the same way as the 7 bit PWMs That is the value set in this 8 bit register determines the basic duty cycle of the waveform A value of 00 results in a continuously Figure 8 1 7 Bit PWM Output Wavef...

Page 69: ... M N 64 256 where M is the content of the 8 bit high order register and N is the content of the 6 bit low order register Using this mechanism a true 14 bit resolution PWM is achieved Figure 8 2 shows the waveform for the 14 bit PWM channel Note that the resulting waveform is periodic on every 64 PWM cycles Figure 8 2 14 Bit PWM Output Waveform M 00 256T M 01 M 7F M FF T 1 CPU clock period 0 476µs ...

Page 70: ...e sequence as shown below LDA BRM_value STA 35 Data put in 6 bit BRM buffer LDA PWM_value STA 36 Load 6 bit BRM and 8 bit PWM register The instruction STA 35 simply puts the 6 bit BRM data in a buffer Output is not affected at this time The instruction STA 36 then puts the total 14 bit data to BRM and PWM register at the same time Output waveform will change accordingly starting from the beginning...

Page 71: ... for fixed character patterns there is a 16 character RAM for user defined patterns This character RAM can be written and read by the CPU but read only by the OSD hardware Since the contents of this character RAM can be changed during run time the user can have a large number of character sets stored in internal ROM or in external ROM EPROM EEPROMs and have them load in via the M bus The character...

Page 72: ... with port PF2 and PF3 respectively HTONE half tone is used to create transparent background effect on the screen OSD registers are divided into four groups with characters register group defining individual character features frame register group defining frame features row register group defining individual row features and finally status register carrying the status of the whole OSD module 9 2 ...

Page 73: ...ound and blinking features for that selected character 9 3 1 Character RAM OSD character RAM is a dual ported RAM consisting of 16x 16x16 8 512 bytes of RAM located from 0400 to 05FF Upon reset the content of character RAM is random Every entry of this 16 entry character RAM occupies 32 consecutive memory bytes always starting at even addresses Users can read and write any byte at any time OSD can...

Page 74: ...bytes Last 8 character register pairs of a row buffer are not used when that row buffer is configured for displaying 16x16 dot characters 0400 05FF 8000 8FFF Character RAM Character ROM EPROM High order bytes Low order bytes 7 0 7 4 3 0 xxx xxx 002 xxx 001 xxx 003 xxx 01E xxx 01F even bytes odd bytes Bits not used when 12x16 dot matrix is selected indicates a character dot exist indicates a charac...

Page 75: ...0 to 15 RAM codes Codes 16 and higher are invalid Figure 9 2 Reserved Character ROM Codes Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset Character Code reg 1 200 ROM RAM CH6 CH5 CH4 CH3 CH2 CH1 CH0 uuuu uuuu Character Attribute reg 1 201 BLNKG BGEN BGCOL2 BGCOL1 BGCOL0 CCOL2 CCOL1 CCOL0 uuuu uuuu Character Code reg 128 2FE ROM RAM CH6 CH5 CH4 CH3 CH2 CH1 CH0 uuuu uuuu Chara...

Page 76: ...s a color from the color palette See Section 9 3 4 9 3 4 Color Palette Registers Ii Ri Gi and Bi bits select the color for color palette i where i 0 1 2 7 I bit is the intensity bit There are 8 color palettes each color palette is one of 16 colors Figure 9 3 shows the color palette organization and Table 9 1 shows the RGB color map Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on r...

Page 77: ... 12x16 matrix is selected a maximum of 32 characters may be displayed for that row Rows selected for 16x16 matrix characters the maximum is 24 characters per row the remaining 8 Table 9 1 RGB Color Map Ii Ri Gi Bi Color 0 0 0 0 Black 0 0 0 1 Blue 0 0 1 0 Green 0 0 1 1 Cyan 0 1 0 0 Red 0 1 0 1 Magenta 0 1 1 0 Yellow 0 1 1 1 White 1 0 0 0 Dark Grey 1 0 0 1 Dark Blue 1 0 1 0 Dark Green 1 0 1 1 Dark C...

Page 78: ... character and row i background dots FBKGCi bit controls the FBKG output pin of the OSD during row i display If FBKGCi is clear FBKG output pin is active during both character dots and background dots of row i If FBKGCi is set FBKG output pin is active only where character dots exist in the character dot matrix including bordering or shadowing dots The FBKG and HTONE pins may be used to create tra...

Page 79: ... mode not character size selection Hence care should be taken when choosing vertical position for a particular row that locates after a row which has character size other than the basic 12x16 or 16x16 setting For example assuming single scan mode if row X has 4Hx4V character size and vertical position of 40 while rowY has basic character size of 1Hx1V and vertical position of 48 then row X will be...

Page 80: ...higher priority or 3 the part of the row display which does not overlap vertical retrace period has been completed This applies to rows immediately before vertical retrace Note that the judgement of overlap is totally based on the vertical position of rows it has nothing to do with character size of rows RiCF bit of Frame Control 3 and Status register will also be set when a row display is termina...

Page 81: ...ong Rows FBKGCi 0 BGEN 1 RiBE 0 FBKGCi 1 BGEN 1 RiBE 1 SHDW 1 HTONE FBKG Char R G B or I Background R G B or I R G B or I Timing signals for 5th line line 4 background dot character dot shadow dot Row i 1 Row i Row j 1 Row j Row i 1 partially overlaps row i Row j 1 and row j completely overlaps therefore only row j is visible a b TPG 79 ...

Page 82: ...yback displayed on one line and all remaining dots after the nth horizontal flyback along with all dots of next line before the n 1 th horizontal flyback displayed on the next line 9 4 4 Row Control Register 1 RiINTE Row interrupt 1 set Row interrupt enabled 0 clear Row interrupt disabled Enable disable interrupt of row i if one of the following conditions occur 1 the part of the row i display whi...

Page 83: ...ting of RiINTE and RiEN 9 4 5 Row Control Register 2 RiCHS1 RiCHS0 Row i character size There are two predefined numbers of total dots that can be displayed on a horizontal line The number of dots per line is a function of character size selection and the size of character dot matrix For the special case of 3Hx3V and 12x16 dot matrix the number of total dots per line is 396 whereas for other combi...

Page 84: ... displayed twice in the same frame The other feature associated with horizontal lines that will also be doubled is the RiVP6 RiVP0 field of Row Vertical Position Registers FADE Display fade enable 1 set Display fade function enabled 0 clear Display fade function disabled The FADE bit controls the sequence of frame display appearance and disappearance When FADE bit is set frame display will gradual...

Page 85: ...o be disappeared are 8 lines 12 lines 14 lines 15 lines and all 16 lines in each disappearance sequence respectively Fade out sequence for a character in a row fitting right into the 16 horizontal line segment is illustrated in Figure 9 7 Fading rate is fixed at 32 frames per sequence Therefore it takes 160 frames to execute the fade function At 60 Hz vertical frequency this will take five plus se...

Page 86: ...A 9 16 MC68HC05T16 ON SCREEN DISPLAY 9 Figure 9 7 Fading Out Sequence Before fading out 1st step 8 lines off 2nd step 12 lines off 3rd step 14 lines off Last step all 16 lines off 4th step 15 lines off TPG 84 ...

Page 87: ...blanking output pin is active high RGBPOL RGB output polarity select 1 set RBG output pins are active low 0 clear RGB output pins are active high IPOL I output polarity select 1 set I intensity output pin is active low 0 clear I intensity output pin is active high 9 5 3 Frame Control 3 and Status Register Bits 7 to 5 are control bits whereas bits 4 to 0 are status bits associated with interrupt A ...

Page 88: ...l flyback interrupt disabled MUTE1 MUTE0 Video mute enable VFLB VFLBK status 1 set Vertical flyback leading edge signal detected 0 clear No Vertical flyback signal detected RiCF Row i display status 1 set Row i display has been terminated 0 clear Row i display has been not terminated Whenever a row display has been terminated the corresponding RiCF flag will be set along with update of CDRC3 CDRC0...

Page 89: ... with continuous conversion A result flag indicates if the comparator output is above or below the analog Input ADC is disabled by setting AD4 to AD0 bits of ADC Control Status register to all 1 s This disable function is mainly for low power applications Figure 10 1 shows a block diagram of the ADC module Figure 10 1 ADC Block Diagram VDD RESULT R 2R ADCIN0 or ADCIN1 AD4 AD3 AD2 AD1 AD0 R R R 2R ...

Page 90: ... bit is set PF4 is configured as ADCIN1 analog input and Port F DDR has no effect on this pin Reading PF4 when configured as an ADC input is zero 10 1 2 ADCIN0 ADCIN0 is a dedicated analog input channel 10 2 Program Example The following example shows how to convert analog input channel 0 ADCIN0 For ADCIN1 conversion change 00 to 20 ADCSR is the ADC Control Status register LDA 00 STA ADCSR ADC Con...

Page 91: ...ed for conversion 0 clear ADCIN0 is selected for conversion AD4 0 ADC Digital Result These bits are written by the user to perform successive approximations in software When a value causes the RESULT bit to change state from the value immediately before or after it AD4 0 are considered to be the digital equivalent of the analog input Note that when AD4 0 are all 1 s ADC is virtually turned off to ...

Page 92: ...MOTOROLA 10 4 MC68HC05T16 ANALOG TO DIGITAL CONVERTER 10 THIS PAGE LEFT BLANK INTENTIONALLY TPG 90 ...

Page 93: ...e programming model of Figure 11 1 The interrupt stacking order is shown in Figure 11 2 11 1 1 Accumulator A The accumulator is a general purpose 8 bit register used to hold operands and results of arithmetic calculations or data manipulations Figure 11 1 Programming model Accumulator Index register Program counter Stack pointer Condition code register Carry borrow Zero Negative Interrupt mask Hal...

Page 94: ...ended to the six least significant register bits to produce an address within the range of 00C0 to 00FF Subroutines and interrupts may use up to 64 decimal locations If 64 locations are exceeded the stack pointer wraps around and overwrites the previously stored information A subroutine call occupies two locations on the stack an interrupt uses five locations 11 1 5 Condition code register CCR The...

Page 95: ... This bit is also affected during bit test and branch instructions and during shifts and rotates 11 2 Instruction set The MCU has a set of 62 basic instructions They can be grouped into five different types as follows Register memory Read modify write Branch Bit manipulation Control The following paragraphs briefly explain each type All the instructions within a given type are presented in individ...

Page 96: ...are to test and branch on the state of any bit within these locations The bit set bit clear bit test and branch functions are all implemented with single instructions For the test and branch instructions the value of the bit tested is also placed in the carry bit of the condition code register Refer to Table 11 4 11 2 4 Read modify write instructions These instructions read a memory location or a ...

Page 97: ... AE 2 2 BE 2 3 CE 3 4 FE 1 3 EE 2 4 DE 3 5 Store A in memory STA B7 2 4 C7 3 5 F7 1 4 E7 2 5 D7 3 6 Store X in memory STX BF 2 4 CF 3 5 FF 1 4 EF 2 5 DF 3 6 Add memory to A ADD AB 2 2 BB 2 3 CB 3 4 FB 1 3 EB 2 4 DB 3 5 Add memory and carry to A ADC A9 2 2 B9 2 3 C9 3 4 F9 1 3 E9 2 4 D9 3 5 Subtract memory SUB A0 2 2 B0 2 3 C0 3 4 F0 1 3 E0 2 4 D0 3 5 Subtract memory from A with borrow SBC A2 2 2 B...

Page 98: ...f half carry clear BHCC 28 2 3 Branch if half carry set BHCS 29 2 3 Branch if plus BPL 2A 2 3 Branch if minus BMI 2B 2 3 Branch if interrupt mask bit is clear BMC 2C 2 3 Branch if interrupt mask bit is set BMS 2D 2 3 Branch if interrupt line is low BIL 2E 2 3 Branch if interrupt line is high BIH 2F 2 3 Branch to subroutine BSR AD 2 6 Table 11 4 Bit manipulation instructions Addressing modes Bit se...

Page 99: ... 79 1 5 69 2 6 Rotate right through carry ROR 46 1 3 56 1 3 36 2 5 76 1 5 66 2 6 Logical shift left LSL 48 1 3 58 1 3 38 2 5 78 1 5 68 2 6 Logical shift right LSR 44 1 3 54 1 3 34 2 5 74 1 5 64 2 6 Arithmetic shift right ASR 47 1 3 57 1 3 37 2 5 77 1 5 67 2 6 Test for negative or zero TST 4D 1 3 5D 1 3 3D 2 4 7D 1 4 6D 2 5 Multiply MUL 42 1 11 Table 11 6 Control instructions Inherent addressing mo...

Page 100: ...BRA BRN BRCLR BRSET BSET BSR CLC 0 CLI 0 CLR 0 1 CMP Condition code symbols H Half carry from bit 3 Tested and set if true cleared otherwise I Interrupt mask Not affected N Negate sign bit Load CCR from stack Z Zero 0 Cleared C Carry borrow 1 Set Not implemented Address mode abbreviations BSC Bit set clear IMM Immediate BTB Bit test branch IX Indexed no offset DIR Direct IX1 Indexed 1 byte offset ...

Page 101: ...on codes INH IMM DIR EXT REL IX IX1 IX2 BSC BTB H I N Z C Condition code symbols H Half carry from bit 3 Tested and set if true cleared otherwise I Interrupt mask Not affected N Negate sign bit Load CCR from stack Z Zero 0 Cleared C Carry borrow 1 Set Not implemented Address mode abbreviations BSC Bit set clear IMM Immediate BTB Bit test branch IX Indexed no offset DIR Direct IX1 Indexed 1 byte of...

Page 102: ...R 3 EXT 3 IX2 2 IX1 1 IX 8 1000 5 5 3 5 3 3 6 5 2 2 3 4 5 4 3 8 1000 BRSET4 BSET4 BHCC LSL LSLA LSLX LSL LSL CLC EOR EOR EOR EOR EOR EOR 3 BTB 2 BSC 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX 9 1001 5 5 3 5 3 3 6 5 2 2 3 4 5 4 3 9 1001 BRCLR4 BCLR4 BHCS ROL ROLA ROLX ROL ROL SEC ADC ADC ADC ADC ADC ADC 3 BTB 2 BSC 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 2 IMM 2 DI...

Page 103: ...le PC indicates the contents of the location pointed to by the PC program counter An arrow indicates is replaced by and a colon indicates concatenation of two bytes For additional details and graphical illustrations refer to the M6805 HMOS M146805 CMOS Family Microcomputer Microprocessor User s Manual or to the M68HC05 Applications Guide 11 3 1 Inherent In the inherent addressing mode all the info...

Page 104: ...AM or I O location EA X PC PC 1 Address bus high 0 Address bus low X 11 3 6 Indexed 8 bit offset In the indexed 8 bit offset addressing mode the effective address is the sum of the contents of the unsigned 8 bit index register and the unsigned byte following the opcode Therefore the operand can be located anywhere within the lowest 511 memory locations This addressing mode is useful for selecting ...

Page 105: ...ared Any read write bit in the first 256 locations of memory including I O can be selectively set or cleared with a single two byte instruction EA PC 1 PC PC 2 Address bus high 0 Address bus low PC 1 11 3 10 Bit test and branch The bit test and branch addressing mode is a combination of direct addressing and relative addressing The bit to be tested and its condition set or clear is included in the...

Page 106: ...MOTOROLA 11 14 MC68HC05L1 CPU CORE AND INSTRUCTION SET 11 THIS PAGE LEFT BLANK INTENTIONALLY TPG 104 ...

Page 107: ...ram counter is loaded with the corresponding interrupt vector see Table 5 1 The effects of the Stop mode on each of the MCU peripheral systems are below 12 1 1 Timer during Stop Mode When Stop mode is entered the timer counter stops counting the internal processor clock is stopped and remains at that particular count value until Stop mode is exited If the exit was caused by reset the counter is fo...

Page 108: ...ling the operation of the PWM module The PWM module hence cannot wake up the CPU 12 1 5 OSD during Stop Mode When Stop mode is entered the internal clock driving most of the OSD logic will be held at a static state disabling the operation of the OSD module If the PLL is not stopped by clearing PLLEN bit the OSD pixel clock will still run causing power consumption in Stop mode The OSD module cannot...

Page 109: ...e the MCU out of Wait mode The operation of the COP system in Wait mode is as for Stop mode but counting is resumed immediately after the exit i e without the 4069 bus cycles The Wait mode power consumption depends on how many systems are active If a non reset exit from the Wait mode is performed e g timer overflow interrupt exit the state of the remaining systems will be unchanged If a reset exit...

Page 110: ...MOTOROLA 12 4 MC68HC05T16 LOW POWER MODES 12 THIS PAGE LEFT BLANK INTENTIONALLY TPG 108 ...

Page 111: ...and the Self Check Bootstrap Mode Figure 13 1 shows the flowchart of entry to these two modes and Table 13 1 shows operating mode selection Figure 13 1 Flowchart of Mode Entering PC2 VDD RESET IRQ SELF CHECK MODE USER MODE 5V 9V N Y Y NORMAL MODE BOOTSTRAP Note Self check mode is for MC68HC05T16 Bootstrap mode is for MC68HC705T16 TPG 109 ...

Page 112: ...hed within first two clock cycles after the rising edge of the reset PC2 can then be used for other purposes After entering the self check mode CPU branches to the self check program and carries out the self check Self check is a repetitive test i e if all parts are checked to be good the CPU will repeat the self check again Therefore the LEDs attached to Port A will be flashing if the device is g...

Page 113: ...3 PC4 PC5 PC6 PC7 PE0 PWM0 PE1 PWM1 PE2 PWM2 PE3 PWM3 PE4 PWM4 PE5 PWM5 PE6 PWM6 PE7 PWM7 PF0PWM8 PF1 PWM9 PF2 I PF3 HTONE PF4 ADCIN1 PF5 SDA PF6 SCL PF7PACIN PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PA0 PA4 PA1 PA5 PA2 PA6 PA3 PA7 9V 2 2µ 10K 5V RESET VCO RP TCAP VDD 10K 10K 2N4400 5V HFLBK VFLBK 10K 5V 1N4148 5V 470K 2K2 2K2 10K 0 1µ 0 1µ ADCIN0 20K 8 x 4K7 8 x 4K7 R G B FBKG TPG 111 ...

Page 114: ...gramming boards are available from Motorola for programming the on chip EPROM please contact your Motorola representative The Program Control register PCR is provided for EPROM programming The function of the EPROM depends on the device operating mode Please contact Motorola for Programming board availability 13 3 2 Program Control Register PCR Table 13 2 Self Check Report PA3 PA2 PA1 PA0 REMARKS ...

Page 115: ...ROM of the MC68HC705T16 is as follows 1 Set the ELAT bit 2 Write the data to be programmed to the address to be programmed 3 Set the PGM bit 4 Delay for the appropriate amount of time 5 Clear the PGM and the ELAT bits The last action may be carried out in a single CPU write operation It is important to remember that an external programming voltage must be applied to the VPP pin while programming b...

Page 116: ...MOTOROLA 13 6 MC68HC05T16 OPERATING MODES 13 THIS PAGE LEFT BLANK INTENTIONALLY TPG 114 ...

Page 117: ...it is recommended that Vin and Vout be constrained to the range VSS Vin or Vout VDD Reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level e g either VSS or VDD 14 2 Thermal Characteristics Voltages referenced to VSS RATINGS SYMBOL VALUE UNIT Supply Voltage VDD 0 3 to 7 0 V Input Voltage Vin VSS 0 3 to VDD 0 3 V Input Voltage at Open Drain pins Vi...

Page 118: ...LOAD 5mA PA0 PA7 PC0 PC3 R G B FBKG PF2 PF7 VOL 0 4 V Input high voltage PA0 PA7 PB0 PB7 PC0 PC7 PE0 PE7 PF0 PF7 TCAP IRQ RESET EXTAL HFLBK VFLBK VIH 0 7xVDD V Input low voltage PA0 PA7 PB0 PB7 PC0 PC7 PE0 PE7 PF0 PF7 TCAP IRQ RESET EXTAL HFLBK VFLBK VIL VSS 0 2xVDD V Data Retention Mode VRM 2 0 V Supply current Run Wait Stop 4 2MHz oscillator on 4 2MHz oscillator off IDD 5 1 100 50 10 2 200 100 m...

Page 119: ...mA PB0 PB7 PC4 PC7 PE0 PE7 PF0 PF1 VOL 0 4 V Output low voltage VDD pins ILOAD 15mA PF5 SDA PF6 SCL VOL 0 4 V Table 14 3 On Screen Display Timings VDD 5 0Vdc 10 VSS 0Vdc temperature range 0 to 70 C CHARACTERISTICS SYMBOL MINIMUM TYPICAL MAXIMUM UNIT Rise Time ILOAD 2K 12pF 0 1 to 0 9VDD R G B FBKG HTONE I tR 5 ns Fall Time ILOAD 2K 12pF 0 9 to 0 1VDD R G B FBKG HTONE I tF 5 ns Dot clock frequency ...

Page 120: ... time tSU STO 2 tCYC Table 14 5 M Bus Interface Output Signal Timing VDD 5 0Vdc 10 VSS 0Vdc temperature range 0 to 70 C CHARACTERISTICS SYMBOL MINIMUM MAXIMUM UNIT START condition hold time tHD STA 8 tCYC START condition setup time for repeated START condition only tSU STA 10 tCYC SCL clock low period tLOW 11 tCYC SCL clock high period tHIGH 11 tCYC SDA SCL rise time see note 1 tR 1 µs SDA SCL fal...

Page 121: ...1 5 tCYC IRQ pulse width low edge triggered tILIH 125 ns IRQ pulse period tILIL see note 1 tCYC ADC comparator stabilization time tSETTLE 10 µs ADC comparator conversion time tCONV 2 3 tCYC Timer resolution Timer TCAP pulse width Timer TCAP period tRESL tTH tTL tTLTL 4 125 see note 2 see note 3 tCYC ns tCYC Notes 1 The minimum period tILIL should not be less than the number of cycle times it takes...

Page 122: ...MOTOROLA 14 6 MC68HC05T16 ELECTRICAL SPECIFICATIONS 14 THIS PAGE LEFT BLANK INTENTIONALLY TPG 120 ...

Page 123: ...g P J Dim Min Max Notes Dim Min Max A 51 69 52 45 1 Dimensions and tolerancing per ANSI Y 14 5 1982 2 All dimensions in mm 3 Dimension L to centre of lead when formed parallel 4 Dimensions A and B do not include mould flash Allowable mould flash is 0 25 mm H 7 62 BSC B 13 72 14 22 J 0 20 0 38 C 3 94 5 08 K 2 92 3 43 D 0 36 0 56 L 15 24 BSC E 0 89 BSC M 0 15 F 0 81 1 17 N 0 51 1 02 G 1 778 BSC P 1 ...

Page 124: ...MOTOROLA 15 2 MC68HC05T16 MECHANICAL SPECIFICATIONS 15 THIS PAGE LEFT BLANK INTENTIONALLY TPG 122 ...

Page 125: ...PUT OUTPUT PORTS MEMORY AND REGISTERS RESETS AND INTERRUPTS TIMERS M BUS SERIAL INTERFACE PULSE ACCUMULATOR PULSE WIDTH MODULATOR ON SCREEN DISPLAY ANALOG TO DIGITAL CONVERTER CPU CORE AND INSTRUCTION SET LOW POWER MODES OPERATING MODES ELECTRICAL SPECIFICATIONS MECHANICAL SPECIFICATIONS ...

Page 126: ...UT PORTS MEMORY AND REGISTERS RESETS AND INTERRUPTS TIMERS M BUS SERIAL INTERFACE PULSE ACCUMULATOR PULSE WIDTH MODULATOR ON SCREEN DISPLAY ANALOG TO DIGITAL CONVERTER CPU CORE AND INSTRUCTION SET LOW POWER MODES OPERATING MODES ELECTRICAL SPECIFICATIONS MECHANICAL SPECIFICATIONS TPG 124 ...

Page 127: ...2 1 3 4 5 6 7 8 9 10 11 12 13 14 15 ...

Page 128: ...om USA EUROPE Motorola Literature Distribution P O Box 20912 Phoenix Arizona 85036 1 800 441 2447 JAPAN Nippon Motorola Ltd Tatsumi SPD JLDC Toshikatsu Otsuki 6F Seibu Butsuryu Center 3 14 2 Tatsumi Koto Ku Tokyo 135 Japan 03 3521 8315 HONG KONG Motorola Semiconductors H K Ltd 8B Tai Ping Industrial Park 51 Ting Kok Road Tai Po N T Hong Kong 852 26629298 ...

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