MC68HC05L1
MOTOROLA
11-9
CPU CORE AND INSTRUCTION SET
11
COM
•
•
◊
◊
1
CPX
•
•
◊
◊
◊
DEC
•
•
◊
◊
•
EOR
•
•
◊
◊
•
INC
•
•
◊
◊
•
JMP
•
•
•
•
•
JSR
•
•
•
•
•
LDA
•
•
◊
◊
•
LDX
•
•
◊
◊
•
LSL
•
•
◊
◊
◊
LSR
•
•
0
◊
◊
MUL
0
•
•
•
0
NEG
•
•
◊
◊
◊
NOP
•
•
•
•
•
ORA
•
•
◊
◊
•
ROL
•
•
◊
◊
◊
ROR
•
•
◊
◊
◊
RSP
•
•
•
•
•
RTI
?
?
?
?
?
RTS
•
•
•
•
•
SBC
•
•
◊
◊
◊
SEC
•
•
•
•
1
SEI
•
1
•
•
•
STA
•
•
◊
◊
•
STOP
•
0
•
•
•
STX
•
•
◊
◊
•
SUB
•
•
◊
◊
◊
SWI
•
1
•
•
•
TAX
•
•
•
•
•
TST
•
•
◊
◊
•
TXA
•
•
•
•
•
WAIT
•
0
•
•
•
Table 11-7 Instruction set (Continued)
Mnemonic
Addressing modes
Condition codes
INH
IMM
DIR
EXT
REL
IX
IX1
IX2
BSC
BTB
H
I
N
Z
C
Condition code symbols
H
Half carry (from bit 3)
◊
Tested and set if true,
cleared otherwise
I
Interrupt mask
•
Not affected
N
Negate (sign bit)
?
Load CCR from stack
Z
Zero
0
Cleared
C
Carry/borrow
1
Set
Not implemented
Address mode abbreviations
BSC
Bit set/clear
IMM
Immediate
BTB
Bit test & branch
IX
Indexed (no offset)
DIR
Direct
IX1
Indexed, 1 byte offset
EXT
Extended
IX2
Indexed, 2 byte offset
INH
Inherent
REL
Relative
TPG
99
Summary of Contents for MC68HC05T16
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Page 14: ...MOTOROLA vi MC68HC05T16 THIS PAGE LEFT BLANK INTENTIONALLY TPG 12 ...
Page 16: ...MOTOROLA viii MC68HC05T16 THIS PAGE LEFT BLANK INTENTIONALLY TPG 14 ...
Page 18: ...MOTOROLA x MC68HC05T16 THIS PAGE LEFT BLANK INTENTIONALLY TPG 16 ...
Page 54: ...MOTOROLA 5 12 MC68HC05T16 TIMERS 5 THIS PAGE LEFT BLANK INTENTIONALLY TPG 52 ...
Page 64: ...MOTOROLA 6 10 MC68HC05T16 M BUS SERIAL INTERFACE 6 THIS PAGE LEFT BLANK INTENTIONALLY TPG 62 ...
Page 110: ...MOTOROLA 12 4 MC68HC05T16 LOW POWER MODES 12 THIS PAGE LEFT BLANK INTENTIONALLY TPG 108 ...
Page 116: ...MOTOROLA 13 6 MC68HC05T16 OPERATING MODES 13 THIS PAGE LEFT BLANK INTENTIONALLY TPG 114 ...