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MELSEC-Q
3 SPECIFICATIONS
3.3 I/O Signals for the PLC CPU
3.3.1 List of I/O signals
Table 3.5 shows a list of the I/O signals for the D/A conversion modules.
The following explanation is mentioned based on the Q68DAV and Q68DAI with 8-
channel analog output (CH.1 to CH.8).
Note that I/O numbers (X/Y) shown in this chapter and thereafter are the values when
the start I/O number for the D/A conversion module is set to 0.
Table 3.5 List of I/O signal
Signal direction
D/A conversion module
CPU module
Signal direction
CPU module D/A conversion module
Device No
Signal name
Device No.
Signal name
X0
Module READY
Y0
Use prohibited
1
X1
Y1
CH1 Output enable/disable flag
X2
Y2
CH2 Output enable/disable flag
X3
Y3
2
CH3 Output enable/disable flag
X4
Y4
2
CH4 Output enable/disable flag
X5
Y5
2
CH5 Output enable/disable flag
X6
Y6
2
CH6 Output enable/disable flag
X7
Use prohibited
1
Y7
2
CH7 Output enable/disable flag
X8
High resolution mode status flag
Y8
2
CH8 Output enable/disable flag
X9
Operating condition setting
completed flag
Y9
Operating condition setting request
XA
Offset/gain setting mode flag
YA
User range writing request
XB
Channel change completed flag
YB
Channel change request
XC
Set value change completed flag
YC
Set value change request
XD
Synchronous output mode flag
YD
Synchronous output request
XE
Use prohibited
1
YE
Use prohibited
1
XF
Error flag
YF
Error clear request
POINT
1 These signals cannot be used by the user since they are used by the system. If
these are turned ON/OFF by the sequence program, the functioning of the D/A
conversion module cannot be guaranteed.
2 For Q62DA, Y3 to Y8 cannot be used.
For Q64DA, Y5 to Y8 cannot be used.