MiTAC 8224, Service Manual

Page: 88 / 167

8224 N/B Maintenance
8224 N/B Maintenance
87
5.1 Intel 945G/945P North Bridge (4)
Analog Display Signals (Intel® 82945G GMCH Only)
Signal Name Type Description
RED O
A
RED Analog Video Output:
This signal is a CRT Analog video output from the internal color
palette DAC. The DAC is designed for a 37.5
Ω
routing impedance;
however, the terminating resistor to ground will be 75
Ω
(e.g., 75
Ω
resistor on the board, in parallel with a 75
Ω
CRT load).
RED# O
A REDB Analog Output:
This signal is an analog video output from the internal color palette
DAC. It should be shorted to the ground plane.
GREEN O
A GREEN Analog Video Output:
This signal is a CRT Analog video output from the internal color
palette DAC. The DAC is designed for a 37.5
Ω
routing impedance:
however, the terminating resistor to ground will be 75
Ω
(e.g., 75
Ω
resistor on the board, in parallel with a 75
Ω
CRT load).
GREEN# O
A GREENB Analog Output:
This signal is an analog video output from the internal color palette
DAC. It should be shorted to the ground plane.
BLUE O
A BLUE Analog Video Output:
This signal is a CRT Analog video output from the internal color
palette DAC. The DAC is designed for a 37.5
Ω
routing impedance;
however, the terminating resistor to ground will be 75
Ω
(e.g., 75
Ω
resistor on the board, in parallel with a 75
Ω
CRT load).
BLUE# O
A BLUEB Analog Output:
This signal is an analog video output from the internal color palette
DAC. It should be shorted to the ground plane.
REFSET O
A Resistor Set:
Set point resistor for the internal color palette DAC. A 255
Ω
1%
resistor is required between REFSET and motherboard ground.
HSYNC O
2.5V
CMOS
CRT Horizontal Synchronization:
This signal is used as the horizontal sync (polarity is programmable)
or “sync interval”. 2.5 V output
.
VSYNC O
2.5V
CMOS
CRT Vertical Synchronization:
This signal is used as the vertical sync (polarity is programmable). 2.5
V output.
DDC_CLK I/O
2.5V
CMOS
Monitor Control Clock:
This signal may be used as the DDC_CLK for a secondary
multiplexed digital display connector.
DDC_DATA I/O
2.5V
CMOS
Monitor Control Data:
This signal may be used as the DDC_Data for a secondary
multiplexed digital display connector.
PCI Express* Interface Signals
Signal Name Type Description
EXP_RXN[15:0]
EXP_RXP[15:0] I/O
PCIE
PCI Express* Receive Differential Pair
EXP_TXN[15:0]
EXP_TXP[15:0] O
PCIE
PCI Express* Transmit Differential Pair
EXP_ICOMPO I
A
PCI Express* Output Current and Resistance Compensation
EXP_COMPI I
A
PCI Express* Input Current Compensation
Unless otherwise specified, PCI Express signals are AC coupled, so the only voltage specified is a
maximum 1.2 V differential swing.
DDR2 DRAM Channel B Interface (Continued)
Signal Name Type Description
SCAS_B# O
SSTL-1.8
Column Address Strobe:
This signal is used with SRAS_B# and SWE_B# (along with
SCS_B#) to define the SDRAM commands.
SWE_B# O
SSTL-1.8
Write Enable:
This signal is used with SCAS_B# and SRAS_B# (along with
SCS_B#) to define the SDRAM commands.
SDQ_B[63:0] I/O
SSTL-1.8
2X
Data Lines:
The SDQ_B[63:0] signals interface to the SDRAM data bus.
SDM_B[7:0] O
SSTL-1.8
2X
Data Mask:
When activated during writes, the corresponding data groups in
the SDRAM are masked. There is one SDM_Bx bit for every data
byte lane.
SDQS_B[7:0] I/O
SSTL-1.8
2X
Data Strobes:
For DDR2, SDQS_Bx and its complement SDQS_Bx# signal
make up a differential strobe pair. The data is captured at the crossing
point of SDQS_Bx and its complement SDQS_Bx# during read and
write transactions.
SDQS_B[7:0]# I/O
SSTL-1.8
2X
Data Strobe Complements:
These are the complementary DDR2 strobe signals.
SCKE_B[3:0] O
SSTL-1.8
Clock Enable:
(1 per Rank). SCKE_Bx is used to initialize the SDRAMs during
power-up, to power-down SDRAM ranks, and to place all SDRAM
ranks into and out of self-refresh during Suspend-to-RAM.
SODT_B[3:0] O
SSTL-1.8
On Die Termination:
Active On-die Termination Control signals for DDR2 devices.
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