8224 N/B Maintenance
8224 N/B Maintenance
27
-- Chip-Erase for PP Mode
•
Single 3.0-3.6V Read and Write Operations
•
Superior Reliability
•
Firmware Hub Hardware Interface Mode
-- 5-signal communication interface supporting byte Read and Write
-- 33 MHz clock frequency operation
-- WP# and TBL# pins provide hardware write protect for entire chip and/or top Boot Block
-- Block Locking Register for all blocks
-- Standard SDP Command Set
-- Data# Polling and Toggle Bit for End-of-Write detection
-- 5 GPI pins for system design flexibility
-- 4 ID pins for multi-chip selection
1.2.9 Memory System
128MB, 256MB, 512MB, 1GB (x64) 200-Pin DDR2 SDRAM SODIMMs
•
JEDEC-standard 200-pin, small-outline, dual in-line memory module (SODIMM)
•
VDD=+1.8V
±
0.1V, VDDQ=+1.8V
±
0.1V
MiTac Secret
Confidential Document
Summary of Contents for 8224
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