RTE-V852-PC
USER’ S MANUAL (Rev. 1.10)
41
9. OTHER CPU RESOURCES
9.1. RESET-
The factors listed below trigger a CPU reset. These factors reset the CPU. They also system-reset
the board control circuit.
•
Power-on reset: Occurs when the power to the board is switched on.
•
Reset request received from JROMEM: Input to the RESET- pin of the JROMEM connector
on the Base board. See Section 3.19 for details.
•
Reset by the SWRESET: Generated by the reset switch (SWRESET) on the rear panel of the
base board.
•
Reset by RESET_SW: Generated by pressing the reset switch (RESET_SW) on the Socket
board.
•
Reset request from the host: Sent via the ISA bus.
The figure below outlines the reset signal generation logic.
ISA_ResetRequest
To CPU
SW_RESET
JROM_EM
RESET-
RESET-
RESET
Socket-Board
Base-Board
RESET_SW
J8-5Pin
9.2. NMI-
An NMI to the CPU occurs as follows:
•
Request received from controller on the Base board: An NMI can be generated by an
interrupt request received from the UART/PRINT controller (TL16C552A) on the Base board (see
Section 6.2).
An NMI can also be generated based on the interrupt request received from the timer (
µ
PD71054)
on the Base board (see Section 6.3). This interrupt is used by the Multi debugger functions such
as the profiler function (see Section 6.11).
Which of the above interrupt requests is to be connected to the NMI can be controlled by
programming (see Section 6.8).
•
Request based on Ready time-over: Time-out Ready occurs when a bus cycle has not been
completed within a certain period. It is possible to generate an NMI request upon the occurrence
of the time-out ready status (see Section 6.8).
•
Request received from JEXT bus: NMI can be generated when the INT signal of the JEXT bus
goes active (see Section 6.8).
