RTE-V852-PC
USER’ S MANUAL (Rev. 1.10)
51
12.2.6. Page Access (Page Mode, Different Row Addresses)
When a different row address from the previously-accessed row address is accessed in page mode,
the RAS signal is deactivated from the start of the cycle and activated again after having waited for a
period equal to the RAS signal precharge time, as shown in the following timing chart.
•
In this timing chart, two ready cycles for the same row address occur after the completion of
RAS precharge of the previous cycle, then a ready cycle for a different row address occurs.
•
Xclk and Zclk represent, respectively, the clock counts for the “ RAS precharge time” and
“ CAS Low width in read access,” which are set in the program (see Section 6.7).
•
When the “ RAS minimum low width” (Yclk) setting is larger, by two or more, than the
“ CAS Low width in read access,” Zclk of the first cycle of the accesses to the same row
address becomes equal to (Yclk - 1).
WE-
CASn-
HIT
RAS-
Sig1: A16 to A19,UBEN-,LBEN-,R/W-
Sig1
DATA
ADDR
ADDR
ADDR
AD0 to AD15
WAIT-
ASTB
T3
TW
TW
TW
TW
TW
TW
T2
T1
T3
TW
TW
T2
T1
CLKOUT
DSTB-
Zclk
T1
T2
T3
DATA
Read Cycle
Read Cycle
Read Cycle
Zclk
Zclk
Xclk
DATA
