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RTE-V852-PC

USER’ S MANUAL (Rev. 1.10)

53

13.4. P30 TO P37

P3[4,6,7]

J3

CPU

TxD

P22

232C

Driver

Buf.

47 k

Ω

RxD

P34

P36

P37

CTS

DSR

P35

RTS

P27

DTR

P3[5]

P3[1,2,3]

47 k

Ω

JPORT3

P3MODE

GND

13.5. P100 TO P103

P10[0:3]

47 k

Ω

JPRT10

CPU

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Summary of Contents for RTE-V852-PC

Page 1: ...RTE V852 PC User s Manual Rev 1 10 Midas lab...

Page 2: ...STORY Date of enforcement Revision Chapter Description August 15 1996 1 00 First issue December 4 1996 1 10 3 5 8 xx Correction JPORT2 Pin Arrangement P21 P21 Correction INT of JEXT Connector Signals...

Page 3: ...ET BOARD SW2 12 3 10 CRYSTAL SOCKET SOCKET BOARD JP1 12 3 11 7 SEGMENT LED SOCKET BOARD LED_P1 13 3 12 LEDS SOCKET BOARD 13 3 13 SWITCH 1 BASE BOARD SW1 13 3 14 SWITCH 2 BASE BOARD SW2 13 3 15 SWITCH...

Page 4: ...T0 INT1 MASK PORT 3F F180H 34 6 11 NMI INT1 REQUEST CLEAR PORTS 3F F190H 3F F1A0H WRITE ONLY 34 6 12 INT0 P22 INTP01 SELECT PORT 3F F200H 35 6 13 INT1 P24 INTP03 SELECT PORT 3F F210H 35 6 14 INT0 P22...

Page 5: ...NTERFACE 47 12 2 1 Outline 47 12 2 2 Signal Description 47 12 2 3 Single Read Normal Mode 48 12 2 4 Single Write Normal Mode 49 12 2 5 Page Access Page Mode Same Row Address 50 12 2 6 Page Access Page...

Page 6: ...O units using local bus connectors provided on the evaluation board 1 1 NUMERIC NOTATION This manual represents numbers according to the notation described in the following table Hexadecimal and bina...

Page 7: ...CONNECTOR OR RTE V852 PC Block Diagram Features ROM Standard 128 Kbytes 64K 16 bit EPROM 1 Maximum 512 Kbytes 128K 16 bit EPROM 1 SRAM 512 Kbytes 64K 16 bit SRAM 4 DRAM 4 8 or 16 Mbytes standard 4 Mb...

Page 8: ...WER JP1 Xtal V852 JPORT10 JPORT1 JPORT0 JPORT2 RTE V852 PC Board Top View 3 1 RESET SWITCH SOCKET BOARD RESET_SW RESET_SW on the Socket board is the reset switch Pressing this switch resets the CPU an...

Page 9: ...the Socket board and on the Base board but it is recommended that the JPOWER connector on the Base board be used The external power should be one rated as listed below Voltage 5 V Current Maximum of 2...

Page 10: ...RT1 pin No Signal name 1 GND 2 GND 3 P17 4 P16 5 P15 6 P14 7 P13 8 P12 9 P11 10 P10 JPORT1 Pin Arrangement JPORT2 pin No Signal name JPORT2 pin No Signal name 1 GND 2 GND 3 P27 SCK2 4 P26 SI2 5 P25 SO...

Page 11: ...2 GND 13 P47 AD7 14 P46 AD6 15 P45 AD5 16 P44 AD4 17 P43 AD3 18 P42 AD2 19 P41 AD1 20 P40 AD0 21 P22 INTP01 22 P21 INTP00 23 RTE_CON IN 24 1M 16M OUT 25 5V IN 26 5V IN J1 J5 Pin Arrangement J2 J6 pin...

Page 12: ...at this connector are converted to the RS 232C level The pin arrangement of the J3 connector is shown below after which the signal assignment is listed For details of the wiring of the connection sign...

Page 13: ...3 RS 232C 3 9 SWITCH 2 SOCKET BOARD SW2 SW2 on the Socket board is connected to CPU Port 0 and can be used freely by the user When a switch contact is OFF it represents 1 When it is ON it represents 0...

Page 14: ...s 3 13 SWITCH 1 BASE BOARD SW1 SW1 is the switch connected to the general purpose input ports and read by software When a switch contact is OFF it represents 1 When it is ON it represents 0 See Sectio...

Page 15: ...est on Base board that is selected with INT1SEL Interrupt is High level SW3 to Interrupt Correspondence 3 16 ROM CAPACITY SWITCHING JUMPER BASE BOARD JP1 JP1 is the jumper to be set according to the c...

Page 16: ...name Input output Function RESET Input Connects the reset request signal from the ROM in circuit debugger The CPU is reset when a Low level signal is input The input is pulled up by a 1 k resistor on...

Page 17: ...e listed For the connection signals when the connectors are connected to the host the table lists the wiring for both the D SUB 9 pins and D SUB 25 pins on the host side Regular cross cable wiring is...

Page 18: ...4 12 GND 13 D5 14 GND 15 D6 16 GND 17 D7 18 GND 19 ACK 20 GND 21 BUSY 22 GND 23 PE 24 GND 25 SELECT 26 NC JPRT Connector Signals 3 22 EXTENSION BUS CONNECTOR BASE BOARD JEXT The JEXT connector is prov...

Page 19: ...M that satisfies the access timing requirements by referring to Section 7 3 The capacity of the connected SIMM can be read through the PIO port See Section 6 6 3 25 ROM SOCKETS The RTE V852 PC has ROM...

Page 20: ...aluation board The switch layout is shown below Switches on the RTE V852 PC Board SW1 on the Base board is a switch for general purpose input ports For the Multi monitor in the factory installed ROM S...

Page 21: ...020xH factory set I O Address Correspondence SW3 on the Base board is set to ON when the interrupt request line on the Base board is connected to a CPU pin Normally set all of contacts 1 to 4 to OFF...

Page 22: ...RTE V852 PC USER S MANUAL Rev 1 10 21 oscillator to JP1 When the clock must be changed see Section 3 10...

Page 23: ...se Reconfirm the I O address of the board by referring to the applicable manual of the PC or the board When the system turns out to be normal turn off the PC power again and put back its housing 4 3 S...

Page 24: ...FFFH Reserved Reserved Access inhibited Reserved Reserved 7F FFFFH 6F FFFFH 5F FFFFH 3F FFFFH 3F F000H 3F EFFFH 80 0000H 70 0000H 60 0000H 40 0000H 20 0000H 1F FFFFH 17 FFFFH 07 FFFFH 0F FFFFH 18 0000...

Page 25: ...the wait count can be set with SYSTEM I O see Section 6 7 For details of the required wait count see Section 7 2 Reserved and access inhibited spaces Do not attempt to access these spaces SYSTEM I O s...

Page 26: ...3F F040H Sets Base board 7 segment LED display data 3F F050H References Base board DIPSW1 3F F060H References status DRAM PD time over flag etc 3F F080H Sets references SRAM wait state 3F F0A0H Sets r...

Page 27: ...F002H IER DLM IER DLM 3F F004H IIR FCR 3F F006H LCR LCR 3F F008H MCR MCR 3F F00AH LSR LSR 3F F00CH MSR MSR 3F F00EH SCR SCR 3F F010H UART CH 2 RBR DLL THR DLL 3F F012H IER DLM IER DLM 3F F014H IIR FC...

Page 28: ...P00 PRINTER NMI P22 INTP01 Maskable interrupts pass through DIP SW3 See Section 9 2 for details of the NMI and Section 9 3 for details of the maskable interrupt UART CH 1 is connected to the JSIO0 con...

Page 29: ...tor program At this time CH 0 also functions as the prescale counter for CH 1 CH 1 can be used as required by the user program The status of the CH 0 and CH 1 outputs can be read from the Status port...

Page 30: ...Bit3 Bit2 Bit1 Bit0 SW1 8 SW1 7 SW1 6 SW1 5 SW1 4 SW1 3 SW1 2 SW1 1 No use No use No use No use TIM1 TIM0 BPS1 BPS0 SW1 8 1 The status of SW1 on the Base board can be read SW1 1 corresponds to switch...

Page 31: ...DRAM The relationship between PD 2 1 and the DRAM capacity is given in table below PD 2 PD 1 DRAM capacity 0 0 4 Mbytes 0 1 Reserved 1 0 16 Mbytes 1 1 8 Mbytes PD 2 1 and DRAM Capacity MEM1M 16M 0 is...

Page 32: ...PRCWIDE0 Function 0 0 Sets the RAS precharge time for DRAM access to 1 clk 0 1 Sets the RAS precharge time for DRAM access to 2 clks 1 0 Sets the RAS precharge time for DRAM access to 3 clks 1 1 Sets...

Page 33: ...the system is reset See Chapter 7 for details of the recommended settings related to the wait state and DRAM See Section 12 2 for an explanation of the significance of the DRAM related settings 6 8 NM...

Page 34: ...RTE V852 PC USER S MANUAL Rev 1 10 33 Reserved 0 This bit is reserved and should be set to 0...

Page 35: ...rrupt request based on communication with ISA bus EXTBUS_NMI Interrupt request received from JEXT bus TOVER_NMI Interrupt request resulting from time over ready occurrence TIMER_NMI Interrupt request...

Page 36: ...to the corresponding interrupt request or to 0 when it need not be generated TIMER_INT1EN Interrupt request issued by TOUT0 of PD71054 TOVER_INT1EN Interrupt request resulting from time over ready occ...

Page 37: ...INT1 is generated by the corresponding interrupt request or set to 0 when it need not be generated Each bit represents the interrupt request status of each interrupt request source and is not affecte...

Page 38: ...5 MHz 1 CLK 2 CLKs 2 CLKs 70 ns 25 MHz 2 CLKs 2 CLKs 2 CLKs 7 4 SYSTEM I O WAIT COUNT The table below lists the recommended wait counts for the SYSTEM I O The SYSTEM I O wait count is determined by th...

Page 39: ...rite cycles must be generated on the external extension bus of the V852 until the recovery time requirement has been satisfied after accessing the TL16C552A or PD71054 Therefore recovery time generati...

Page 40: ...s bus signal which is originally the CPU address signal received at a buffer BHE Output Byte high enable signal which is originally the CPU UBE signal received at a buffer D 0 15 Input output Data bus...

Page 41: ...p time 15 T6 RD data hold time 0 T7 RD READY WAIT setup time 0 T8 RD READY setup time 0 T9 RD READY hold time 0 T10 WR address setup time 0 T11 WR address hold time 20 T12 WR cycle time 50 T13 WR cycl...

Page 42: ...rd Base Board RESET_SW J8 5Pin 9 2 NMI An NMI to the CPU occurs as follows Request received from controller on the Base board An NMI can be generated by an interrupt request received from the UART PRI...

Page 43: ...10 for an explanation of the masking method The following procedure must be applied when an NMI occurs Mask the NMI by means of hardware by setting NMIMASK of the NMI mask port to 1 Determine the NMI...

Page 44: ...request received from the timer PD71054 on the Base board see Sections 6 3 and 6 11 Request based on Ready time over Time out Ready occurs when a bus cycle has not been completed within a certain peri...

Page 45: ...INTP03 SW3 4 INT1_MASK 9 4 PORT Among the CPU ports P4 0 7 P5 0 7 P6 0 3 and P9 0 6 which are related to the external extension bus are used for connection to the Base board Other ports including P0 0...

Page 46: ...s set to 1F 7FFCH immediately before the monitor work RAM by the monitor _INIT_SP can be changed in the Multi environment 10 4 REMOTE CONNECTION Either serial or ISA bus connection can be selected for...

Page 47: ...art the HELP command lists all usable commands Example HELP SFR Displays help messages for the SFR command 11 2 INIT Format INIT Initializes the RTE environment Usually this command should not be used...

Page 48: ...es it possible to reduce the access time for continuous access to the same row address If however an access to another row address is generated the access time becomes slower when continuous access fa...

Page 49: ...of these cycles is kept waiting during RAS precharging Xclk Yclk and Zclk represent respectively the clock counts for the RAS precharge time RAS Low width and CAS Low width in read access which are se...

Page 50: ...these cycles is kept waiting during RAS precharging Xclk and Yclk represent respectively the clock counts for the RAS precharge time and RAS Low width which are set in the program see Section 6 7 The...

Page 51: ...ee Section 6 7 The CAS Low width in write access is always one clock When the RAS minimum low width Yclk setting is larger by two or more than the CAS Low width in read access Zclk of the first cycle...

Page 52: ...of RAS precharge of the previous cycle then a ready cycle for a different row address occurs Xclk and Zclk represent respectively the clock counts for the RAS precharge time and CAS Low width in read...

Page 53: ...describes the connection schemes of the CPU ports which are connected to the connectors on the Socket board 13 1 P00 TO P07 P0 0 7 SW2 JPORT0 47 k CPU 13 2 P10 TO P17 P1 0 7 74ACT540 JPORT1 CPU 47 k 1...

Page 54: ...PC USER S MANUAL Rev 1 10 53 13 4 P30 TO P37 P3 4 6 7 J3 CPU TxD P22 232C Driver Buf 47 k RxD P34 P36 P37 CTS DSR P35 RTS P27 DTR P3 5 P3 1 2 3 47 k JPORT3 P3MODE GND 13 5 P100 TO P103 P10 0 3 47 k JP...

Page 55: ...RTE V852 PC USER S MANUAL Rev 1 10 54 Memo RTE V852 PC User s Manual M662MNL02 Created on August 15 1996 Rev 1 00 Midas lab...

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