RTE-V852-PC
USER’ S MANUAL (Rev. 1.10)
43
9.3. MASKABLE INTERRUPTS (INT0(P22/INTP01), INT1 (P24/INTP03))
The factors listed below trigger INT0 (P00/INTP00). See Section 6.12 for details of selecting an
interrupt.
•
Request from controller on the Base board: INT0 (P22/INTP01) can be generated by the
UART-CH#1 or PRINTER interrupt request received from the UART/PRINT controller
(TL16C552A) on the Base board (see Section 6.2).
•
Request from ISA bus: INT0 (P22/INTP01) can be used for controlling communications via the
ISA bus.
The factors listed below trigger INT1 (P24/INTP03). See Section 6.13 for details of selecting an
interrupt.
•
Request received from controller on the Base board: INT1 (P24/INTP03) can be generated
by an interrupt request received from the timer (
µ
PD71054) on the Base board (see Sections 6.3
and 6.11).
•
Request based on Ready time-over: Time-out Ready occurs when a bus cycle has not been
completed within a certain period. It is possible to generate INT1 (P24/INTP03) upon the
occurrence of the time-out ready signal (see Section 6.11).
It is possible to mask INT0/INT1 by means of hardware. See Section 6.10 for an explanation of the
masking method.
The following procedure must be applied when an INT0/INT1 occurs.
À
Mask the INT0/INT1, by means of hardware, by setting INT0MASK or INT1MASK of the
NMI/INT0/INT1 mask port to “ 1” .
Á
Determine the INT0/INT1 request source. This can be identified at the INT0 or INT1 status port
(see Sections 6.14 and 6.15).
Â
Clear the request by performing interrupt processing for the request source.
Ã
Reset the mask by setting INT0MASK or INT1MASK of the NMI/INT0/INT1 mask port to “ 0” .
Ä
Return from NMI processing.
