RTE-V852-PC
USER’ S MANUAL (Rev. 1.10)
40
RD-
A[0..19]
BHE-
T1
T2
Write cycle
Read cycle
READY
D[0..15]
WR-
T9
T8
Dout
High
T7
Din
RD-
A[0..19]
BHE-
T10
T12
T15
READY
D[0..15]
WR-
T17
T16
T18
T6
High
T14
T3
T4
T11
T13
T5
JEXT Bus Cycle
Symbol
Description
Min. (ns)
Max. (ns)
T1
RD address setup time
0
T2
RD address hold-up time
0
T3
RD cycle time
50
T4
RD cycle interval
20
T5
RD data setup time
15
T6
RD data hold time
0
T7
RD READY WAIT setup time
0
T8
RD READY setup time
0
T9
RD READY hold time
0
T10
WR address setup time
0
T11
WR address hold time
20
T12
WR cycle time
50
T13
WR cycle interval
20
T14
WR data delay time
20
T15
WR data hold time
20
T16
WR READY WAIT setup time
0
T17
WR READY setup time
0
T18
WR READY hold time
0
JEXT Bus AC Specifications
2
1
3
4
5
6
7
8
20
19
18
17
16
15
14
13
12
11
10
9
22
21
23
24
25
26
27
28
40
39
38
37
36
35
34
33
32
31
30
29
41
43
44
45
46
47
48
60
59
58
57
56
55
54
53
52
51
50
49
41
JEXT Pin Arrangement
