Key Components Description and Operation
UG0617 User Guide Revision 4.0
18
4.4.4
SERDES PCIe5 Interface
Lane 0 is connected to the SMA connectors, Lane 1 (RXD) is connected to Lane 2 (TXD), Lane 2 (RXD)
is connected to Lane 1 (TXD), and Lane 3 (TXD and RXD) is connected to the Marvell PHY device of
Port 0. The reference clock is connected from the 125 MHz differential clock oscillator and optionally
connected from the SMA connectors.
The following figure shows the SERDES PCIe5 interface of the RTG4 Development Board.
Figure 10 •
SERDES_PCIe5 Interface
For more information, see the Board Level Schematics document (provided separately).
4.5
Marvell PHY (88E1340S)
The RTG4 Development Kit uses the on-board Marvell Alaska PHY device (88E1340S) for Ethernet
communications at 100 Mbps or 1000 Mbps. The 88E1340S device has four independent gigabit
Ethernet transceivers, but the board uses only one transceiver. The transceiver performs all the physical
layer functions for 100BASE-TX and 1000BASE-T full- or half-duplex Ethernet on a CAT5 twisted-pair
cable. The PHY device is connected to a user-provided Ethernet cable through an RJ45 connector with
built-in magnetics.
The 88E1340S device supports the quad SGMII for direct connection to a RTG4 chip (see
Figure 11,
page 19).
It is configured through the CONFIG [3:0] and CLK_SEL [1:0] pins.
The CLK_SEL [1:0] pin is used to select the reference clock input option. On the board, the status of the
CLK_SEL0 and CLK_SEL1 pins is high. REF_CLK is a 25 MHz reference differential clock input (Y3). It
consists of LVDS differential inputs with a 100
Ω
differential internal termination resistor.
•
RCLK—Gigabit recovered clock
•
SCLK—25 MHz synchronous input reference clock
Expected reference clock (REF_CLK) specifications:
•
Voltage level: 3.3 (± 0.3) V
•
Differential LVDS
Lane0/ RXD
Lane0/
TXD
Lane3/RXD
RTG4
SERDES_PCIe5
Lane1/ RXD
Lane2/ TXD
Lane2/ RXD
Lane1/ TXD
Lane3/
TXD
125 MHz
Magnetics/
Jack – RJ45
Lane0/ RXD
Lane0/ TXD
Lane1/ RXD
Lane2/ TXD
Lane2/ RXD
Lane1/ TXD
Lane3/ TXD
Lane3/ RXD
REFCLK
RTG4
SERDES_PCIe5
J30
0
1
2
3
P0
Marvell PHY
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