Key Components Description and Operation
UG0617 User Guide Revision 4.0
14
TXD pairs are capacitively coupled to the RTG4 device. Series AC-coupling capacitors are used to set
the common-mode voltage.
Mount R365 and R363 (remove R370 and R361) to source the clock from the100 MHz differential
oscillator to the reference clock.
For more information, see the Board Level Schematics document (provided separately).
4.4.2
SERDES1 and SERDES2 Interfaces
The SERDES1 and SERDES2 interfaces (lanes 0/1/2/3) are routed to the FMC connector J12.
Reference clocks of the SERDES1 and SERDES2 interfaces are routed from the FMC connector.
The following figure shows the SERDES1 and SERDES1 interfaces of the RTG4 Development Board.
Figure 8 •
SERDES1 and SERDES2 Interfaces
According to the VITA-57 standard, series capacitors should be placed on the daughter board for TXD
and RXD pins.
For more information, see the Board Level Schematics document (provided separately).
SERDES1 Lane0/
RXD
SERDES1 Lane1/
RXD
SERDES1 Lane2/
RXD
SERDES1 Lane3/
RXD
SERDES1 Lane0/
TXD
SERDES1 Lane1/
TXD
SERDES1 Lane2/
TXD
SERDES1 Lane3/
TXD
SERDES2 Lane0/
RXD
SERDES2 Lane1/
RXD
SERDES2 Lane0/
TXD
SERDES2 Lane1/
TXD
SERDES2 Lane2/
TXD
SERDES2 Lane3/
TXD
SERDES2 REFCLK0
FMC
Connector
HPC2
(J12)
SERDES1 Lane0/ RXD
SERDES1 Lane1/ RXD
SERDES1 Lane2/ RXD
SERDES1 Lane3/ RXD
SERDES2 Lane0/ RXD
SERDES2 Lane1/ RXD
SERDES2 Lane2/ RXD
SERDES2 Lane3/ RXD
SERDES1 Lane0/ TXD
SERDES1 Lane1/ TXD
SERDES1 Lane2/ TXD
SERDES1 Lane3/ TXD
SERDES2 Lane0/ TXD
SERDES2 Lane1/ TXD
SERDES2 Lane2/ TXD
SERDES2 Lane3/ TXD
SERDES1 REFCLK0
SERDES2 REFCLK0
RTG4
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