PIC24FV16KM204 FAMILY
DS33030A-page 168
Advance Information
2013 Microchip Technology Inc.
REGISTER 14-6:
SSPxCON3: MSSPx CONTROL REGISTER 3 (SPI MODE)
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ACKTIM
PCIE
SCIE
BOEN
(
SDAHT
SBCDE
AHEN
DHEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-8
Unimplemented:
Read as ‘
0
’
bit 7
ACKTIM:
Acknowledge Time Status bit (I
2
C™ mode only)
Unused in SPI mode.
bit 6
PCIE
: Stop Condition Interrupt Enable bit (I
2
C mode only)
Unused in SPI mode.
bit 5
SCIE
: Start Condition Interrupt Enable bit (I
2
C mode only)
Unused in SPI mode.
bit 4
BOEN:
Buffer Overwrite Enable bit
)
In SPI Slave mode:
1
= SSPxBUF updates every time that a new data byte is shifted in, ignoring the BF bit
0
= If a new byte is received with the BF bit of the SSPxSTAT register already set, the SSPOV bit of
the SSPxCON1 register is set and the buffer is not updated
bit 3
SDAHT:
SDAx Hold Time Selection bit (I
2
C mode only)
Unused in SPI mode.
bit 2
SBCDE:
Slave Mode Bus Collision Detect Enable bit (I
2
C Slave mode only)
Unused in SPI mode.
bit 1
AHEN:
Address Hold Enable bit (I
2
C Slave mode only)
Unused in SPI mode.
bit 0
DHEN:
Data Hold Enable bit (Slave mode only)
Unused in SPI mode.
Note 1:
For daisy-chained SPI operation: Allows the user to ignore all but the last received byte. SSPOV is still set
when a new byte is received and BF =
1
, but hardware continues to write the most recent byte to
SSPxBUF.
Summary of Contents for PIC24FV16KM204 FAMILY
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