PIC24FV16KM204 FAMILY
DS33030A-page 124
Advance Information
2013 Microchip Technology Inc.
bit 7
CLKLOCK:
Clock Selection Lock Enable bit
If FSCM is Enabled (FCKSM1 =
1
):
1
= Clock and PLL selections are locked
0
= Clock and PLL selections are not locked and may be modified by setting the OSWEN bit
If FSCM is Disabled (FCKSM1 =
0
):
Clock and PLL selections are never locked and may be modified by setting the OSWEN bit.
bit 6
Unimplemented:
Read as ‘
0
’
bit 5
LOCK:
PLL Lock Status bit
)
1
= PLL module is in lock or PLL module start-up timer is satisfied
0
= PLL module is out of lock, PLL start-up timer is running or PLL is disabled
bit 4
Unimplemented:
Read as ‘
0
’
bit 3
CF:
Clock Fail Detect bit
1
= FSCM has detected a clock failure
0
= No clock failure has been detected
bit 2
SOSCDRV
: Secondary Oscillator Drive Strength bit
)
1
= High-power SOSC circuit is selected
0
= Low/high-power select is done via the SOSCSRC Configuration bit
bit 1
SOSCEN:
32 kHz Secondary Oscillator (SOSC) Enable bit
1
= Enables the secondary oscillator
0
= Disables the secondary oscillator
bit 0
OSWEN:
Oscillator Switch Enable bit
1
= Initiates an oscillator switch to the clock source specified by the NOSC<2:0> bits
0
= Oscillator switch is complete
REGISTER 9-1:
OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED)
Note 1:
Reset values for these bits are determined by the FNOSCx Configuration bits.
2:
This bit also resets to ‘
0
’ during any valid clock switch or whenever a non-PLL Clock mode is selected.
3:
When SOSC is selected to run from a digital clock input, rather than an external crystal (SOSCSRC =
0
),
this bit has no effect.
Summary of Contents for PIC24FV16KM204 FAMILY
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