7I90HD 14
OPERATION
SPI HOST INTERFACE
DATA TRANSFER SEQUENCE
Example 1: Read 3 doublewords starting at 0x1000 with increment.
Master asserts /CS
Master sends 0x1000A830
7I90HD echos dummy data
Master sends 0x00000000
7I90HD echos register data @0x1000
Master sends 0x00000000
7I90HD echos register data @0x1004
Master sends 0x00000000
7I90HD echos register data @0x1008
Master de-asserts /CS
Example 2: Write 4 doublewords (A,B,C,D) to location 0x600C:
Master asserts /CS
Master sends 0x600CB040
7I90HD echos dummy data
Master sends 0x0000000A
7I90HD echos dummy data
Master sends 0x0000000B
7I90HD echos dummy data
Master sends 0x0000000C
7I90HD echos dummy data
Master sends 0x0000000D
7I90HD echos dummy data
Master de-asserts /CS
The master may de-assert /CS between frames or leave it asserted without affecting
the SPI interface behavior as long as the CS idle time does not exceed the burst timeout
value.
BURST TIMEOUT
Because the 7I90HD’s SPI interface supports burst transfers of programmable
length, its possible that an aborted or incorrect command could leave the 7I90HD in an
unknown state. To recover from this condition, the 7I90HDs SPI interface has a timeout
on bursts. The default timeout is 50 uSec. If /CS is de-asserted for 50 usec, the SPI
interface will be reset (and any pending burst aborted) so that it expects a SPI header (a
new command) as the next frame. A side effect of this timeout is that a burst transfer must
never de-assert /CS for longer than 50 uSec during a burst.
SPI SIGNAL INTEGRITY
When using the SPI interface, signal quality is of very high importance. For best
signal quality you should always use a flatcable with all 8 ground wires on P4 connected
to the SPI master. In addition, the SPI master clock signal should be series terminated so
that it has a 130 Ohm total source resistance to match the flat cable impedance. This
typically means adding a ~47 Ohm series resistor in the SPI CLK line at the master end.
