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Mesa 7I90HD, Manual

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Mesa 7I90HD Manual Download Page 29

7I90HD 25

REFERENCE INFORMATION

LBP16

CRC

If CRCs are enabled all transmitted and received messages have a 16 bit CRC

appended to the message. The CRC polynomial is X^16 +X^12 +X^5 +1 (CRC-CCITT) The
varient used is CRC-CCITT-KERMIT.

FRAMING

Packet framing in accomplished with timed gaps in transmitted data. Default packet

frame timeout is 2 character times at high baud rates and 25 character times at 115200
baud.

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Summary of Contents for 7I90HD

Page 1: ...7I90HD EPP SPI SERIAL ANYTHING I O MANUAL Version 1 7...

Page 2: ...This page intentionally not blank...

Page 3: ...OWER CONNECTOR PIN OUT 8 JTAG CONNECTOR PIN OUT 8 EPP SPI CONNECTOR PIN OUT 9 RS 422 CONNECTOR PIN OUT 10 OPERATION 11 FPGA 11 HOST COMMUNICATION 11 EPP 11 SPI 11 LBP 11 LBP16 11 LBP HOST INTERFACE SS...

Page 4: ...COMMANDS 24 LBP16 CRC 25 LBP16 FRAMING 25 INFO AREA 26 INFO AREA MEMSIZES FORMAT 26 INFO AREA MEMRANGES FORMAT 27 INFO AREA ACCESS 28 7I90HD SUPPORTED MEMORY SPACES 29 SPACE0 HOSTMOT2 REGISTERS 29 SP...

Page 5: ...rt Serial remote I O BISS SSI SPI UART interfaces and more All motion control firmware is open source and easily modified to support new functions or different mixes of functions All I O bits are 5V t...

Page 6: ...ghtercards use 5V JUMPER POS FUNCTION W6 UP 5V DAUGHTERCARD AND PULLUP POWER W6 DOWN 3 3V DAUGHTERCARD AND PULLUP POWER 5V I O TOLERANCE The FPGA used on the 7I90HD has a 4V absolute maximum input vol...

Page 7: ...tly restored to the UP position to allow the primary flash memory to be re written W3 MEMORY UP PRIMARY NORMAL OPERATION DOWN SECONDARY BACKUP SECONDARY FLASH WRITE ENABLE To prevent accidentally over...

Page 8: ...7I90HD 4 CONNECTORS CONNECTOR LOCATIONS AND DEFAULT JUMPER POSITIONS...

Page 9: ...NC PIN FUNC 1 IO0 2 GND 3 IO1 4 GND 5 IO2 6 GND 7 IO3 8 GND 9 IO4 10 GND 11 IO5 12 GND 13 IO6 14 GND 15 IO7 16 GND 17 IO8 18 GND 19 IO9 20 GND 21 IO10 22 GND 23 IO11 24 GND 25 IO12 26 GND 27 IO13 28 G...

Page 10: ...7 IO27 8 GND 9 IO28 10 GND 11 IO29 12 GND 13 IO30 14 GND 15 IO31 16 GND 17 IO32 18 GND 19 IO33 20 GND 21 IO34 22 GND 23 IO35 24 GND 25 IO36 26 GND 27 IO37 28 GND 29 IO38 30 GND 31 IO39 32 GND 33 IO40...

Page 11: ...7 IO51 8 GND 9 IO52 10 GND 11 IO53 12 GND 13 IO54 14 GND 15 IO55 16 GND 17 IO56 18 GND 19 IO57 20 GND 21 IO58 22 GND 23 IO59 24 GND 25 IO60 26 GND 27 IO61 28 GND 29 IO62 30 GND 31 IO63 32 GND 33 IO64...

Page 12: ...TOP SQUARE PAD 2 GND BOTTOM ROUND PAD JTAG CONNECTOR PINOUT P6 is a JTAG programming connector This is normally used only for debugging or if both EEPROM configurations have been corrupted In case of...

Page 13: ...e end and a 26 pin female header on the other end to interface the hosts printer port to the 7I90HD P4 PIN DB25 PIN SIGNAL P4 PIN DB25 PIN SIGNAL 1 1 STROBE 2 14 AUTOFD 3 2 PD0 4 15 FAULT 5 3 PD1 6 16...

Page 14: ...2 RXB TO 7I90HD ORANGE 3 TXA FROM 7I90HD GREEN WHITE 4 GND EITHER BLUE 5 GND EITHER BLUE WHITE 6 TXB FROM 7I90HD GREEN 7 5V EITHER BROWN WHITE 5V if W5 is up 8 5V EITHER BROWN 5V if W5 is up J1s pinou...

Page 15: ...ows the 7I90HD to be use as a simple 72 I O Smart Serial slave for remote TTL level interfacing LBP16 LBP16 is a simple binary serial master slave protocol suited to larger data blocks than LBP LBP16...

Page 16: ...FPGA PIN DIRECTION 1 WRITE STROBE 40 TO FPGA 2 DSTROBE AUTOFD 41 TO FPGA 8 ASTROBE SELECTIN 48 TO FPGA 21 WAIT BUSY 61 FROM FPGA 3 D0 D0 43 BIDIR 5 D1 D1 45 BIDIR 7 D2 D2 47 BIDIR 9 D3 D3 51 BIDIR 11...

Page 17: ...A A A A A A A A A A A A A A A A C C C C I N N N N N N N X X X X The first 16 bits A in the table above are the HostMot2 register address byte address MSb first The next 4 bits C are the command Curren...

Page 18: ...not exceed the burst timeout value BURST TIMEOUT Because the 7I90HD s SPI interface supports burst transfers of programmable length its possible that an aborted or incorrect command could leave the 7I...

Page 19: ...selectable options Low_Baud and CRC_Disable These options are intended to simplify testing and allow 115200 baud rate for firmware updating via normal USB serial adapters These options are selected b...

Page 20: ...als from a 9 pin PC serial port or USB RS 232 adapter to the 7I90HD s RS 422 signals via a one ended CAT5 cable A single resistor between RS 232 TXD and RS 422 RXB is needed to prevent overloading the...

Page 21: ...EEPROMS The second backup method relies on the fact that there are two flash memories on the 7I90HD card selectable via jumper W3 If a configuration fails in such a way that it loads correctly has a...

Page 22: ...0x000000 BOOT BLOCK 0x010000 FALLBACK CONFIGURATION BLOCK 0 0x020000 FALLBACK CONFIGURATION BLOCK 1 0x030000 FALLBACK CONFIGURATION BLOCK 2 0x040000 FALLBACK CONFIGURATION BLOCK 3 0x050000 FALLBACK C...

Page 23: ...ity can also write configuration files via the EPP interface These files depend on a simple SPI interface built into both the standard user FPGA bitfiles and the fallback bitfile If mesaflash is run w...

Page 24: ...nning the configuration utility and re writing the user configuration FAILURE TO CONFIGURE The 7I90HD should configure its FPGA within a fraction of a second of power application If the FPGA card fail...

Page 25: ...able I O levels for interfacing with different logic families The 7I90HD does not support use of the I O standards that require input reference voltages All standard Mesa configurations use LVTTL leve...

Page 26: ...guration with 4 PWM outputs 4 encoder inputs 8 hardware stepgenerators a watchdog timer and GPIO SVST8_8IM2 SVST8_8IM2 is a 8 axis servo 8 axis stepmotor configuration with 8 PWM outputs 8 encoder inp...

Page 27: ...S Each of the configurations has an associated file with file name extension pin that describes the FPGA functions included in the configuration and the I O pinout These are plain text files that can...

Page 28: ...ter C Indicates if memory space itself C 0 or associated info area for the memory will be accessed C 1 M Is the 3 bit memory space specifier 000b through 111b S Is the transfer element size specifier...

Page 29: ...a 16 bit CRC appended to the message The CRC polynomial is X 16 X 12 X 5 1 CRC CCITT The varient used is CRC CCITT KERMIT FRAMING Packet framing in accomplished with timed gaps in transmitted data De...

Page 30: ...it read access is allowed to the info area 0000 COOKIE 0X5A0N WHERE N ADDRESS SPACE 0 7 0002 MEMSIZES 0004 MEMRANGES 0006 ADDRESS POINTER 0008 SPACENAME 0 1 000A SPACENAME 2 3 000C SPACENAME 4 5 000E...

Page 31: ...RMATION LBP16 INFO AREA MEMRANGES FORMAT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 E E E E E P P P P P S S S S S S E Is erase block size P Is Page size S Ps address range Ranges are 2 E 2 P 2 S E and P ar...

Page 32: ...is the low and high bytes of the address Ispace 0 read with address NN61LLHH HostMot2 space Ispace 0 read NN21 Ispace 1 read with address NN65LLHH Unused Ispace 1 read NN25 Ispace 2 read with address...

Page 33: ...t order for convenienc5901e In the hex command examples the NN is the count increment field of the LBP16 command and the LLHH is the low and high bytes of the address SPACE 0 HOSTMOT2 REGISTERS This a...

Page 34: ...ress IDROM starts at 0x0400 Example write 3 GPIO ports starting at 0x1000 83C20010AAAAAAAABBBBBBBBCCCCCCCC 83 83 NN 3 Inc bit so address is incremented after each access C2 Write to space 0 with addre...

Page 35: ...only flash ID register 000C SEC_ERASE 32 bit write only sector erase register Unlike other memory spaces flash memory space is accessed indirectly by writing the address register FL_ADDR and then read...

Page 36: ...LBP packet 1450 bytes Writes and erases require that the EEPROMWEna be set to 5A03 Note that EEPROMWEna is cleared at the end of every LPB packet so the write EEPROMWEna command needs to prepended to...

Page 37: ...h sector 0x00010000 01D91A00035A Write EEPROMWEna with 0x5A03 01CE000000000100 Write flash address with 0x 00010000 01CE0C0000000000 Write sector erase command with dummy 32 bit data 0 014E0000 Read f...

Page 38: ...eads the free running hardware microsecond timer It is useful for timing internal 7I90 operations Writes to the uSTimeStamp register are a no op The WaituS register delays processing for the specified...

Page 39: ...and TXUDPCount can be used as sequence numbers to verify packet reception and transmission Space 6 read with address NN59LLHH Space 6 write with address NND9LLHHDDDD Space 6 read NN19 Space 6 write N...

Page 40: ...e numbers 001A EEPROMWEna Must be set to 5A0N enable EEPROM or flash writes or erases N is memory space of EEPROM or flash Note that this is cleared at the end of every packet 001C LBPReset Setting th...

Page 41: ...7 LAYOUT ADDRESS DATA 0000 CardNameChar 0 1 0002 CardNameChar 2 3 0004 CardNameChar 4 5 0006 CardNameChar 6 7 0008 CardNameChar 8 9 000A CardNameChar 10 11 000C CardNameChar 12 13 000E CardNameChar 14...

Page 42: ...ON 3A Depends on FPGA configuration and external load INPUT VOLTAGE 3 3V mode 0 6V 4V INPUT VOLTAGE 5V mode 0 6V 7V VOL 0 5V 20 mA sink VOH 2 8V 20 mA source 3 3V mode RS 422 DATA RATE 10 MBaud MAX 5V...

Page 43: ...7I90HD 39 REFERENCE INFORMATION CARD DRAWING...

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