7I90HD 2
HARDWARE CONFIGURATION
GENERAL
Hardware setup jumper positions assume that the 7I90HD card is oriented in an
upright position, that is, with the EPP/SPI connector pointing towards the left.
CONNECTOR POWER
The 7I90HD has the option to supply 5V or 3.3V power from 7I90HDs I/O
connectors to daughtercards.
The power option is individually selectable for each of the three I/O connectors. The
5V power is protected by per connector PTC devices so will not cause damage to the
7I90HD or system if accidentally shorted. The daughtercard voltage also selects the pullup
resistor supply voltage for each connector. Note that all current Mesa daughtercards use
5V.
JUMPER
POS
FUNCTION
W6
UP
5V DAUGHTERCARD AND PULLUP POWER
W6
DOWN
3.3V DAUGHTERCARD AND PULLUP POWER
5V I/O TOLERANCE
The FPGA used on the 7I90HD has a 4V absolute maximum input voltage
specification. To allow interfacing with 5V inputs, the 7I90HD has bus switches on all I/O
pins. The bus switches work by turning off when the input voltage exceeds a preset
threshold. The 5V I/O tolerance option is the default and should normally be left enabled.
For high speed applications where only 3.3V maximum signals are present and
overshoot clamping is desired, the 5V I/O tolerance option can be disabled. W1 controls
the 5V I/O tolerance option. When W1 is on the default UP position, 5V tolerance mode
is enabled. When W1 is in the DOWN position, 5V tolerance mode is disabled. Note that
W1 controls 5V tolerance on all I/O connectors.
