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DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver

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Table 13-8. Receive RMII Interface

(Note 1,

Figure 13-4

)

10Mbps 100Mbps

PARAMETER SYMBOL

MIN TYP MAX

UNITS

REF_CLK Frequency

50MHz

±50ppm

50MHz

±50ppm

MHz

REF_CLK

Period

t1 20

20 ns

REF_CLK Low Time

REF_CLK High Time

RXD, CRS_DV to REF_CLK Setup
Time

t8 5

5 ns

REF_CLK to RXD, CRS_DV Hold
Time

t9 5

5 ns

Note 1:

Timing parameters in this table are guaranteed by design (GBD).

Figure 13-4. Receive RMII Interface Timing

REF_CLK

RXD[3:0]

CRS_DV

Summary of Contents for DS33R11

Page 1: ...ontrol Integrated T1 E1 J1 Framer and LIU HDLC LAPS Encapsulation with Programmable FCS and Interframe Fill Committed Information Rate Controller Provides Fractional Allocations in 512kbps Increments...

Page 2: ...ARY 18 5 MAJOR OPERATING MODES 19 6 BLOCK DIAGRAMS 20 7 PIN DESCRIPTIONS 25 7 1 PIN FUNCTIONAL DESCRIPTION 25 8 FUNCTIONAL DESCRIPTION 41 8 1 PROCESSOR INTERFACE 42 8 1 1 Read Write Data Strobe Modes...

Page 3: ...78 10 7 1 Line Code Violation Counter TR LCVCR 78 10 7 2 Path Code Violation Count Register TR PCVCR 79 10 7 3 Frames Out of Sync Count Register TR FOSCR 80 10 7 4 E Bit Counter TR EBCR 80 10 8 DS0 M...

Page 4: ...IZER 112 10 29FRACTIONAL T1 E1 SUPPORT 112 10 30T1 E1 J1 TRANSMIT FLOW DIAGRAMS 113 11 DEVICE REGISTERS 117 11 1 REGISTER BIT MAPS 118 11 1 1 Global Ethernet Mapper Register Bit Map 118 11 1 2 Arbiter...

Page 5: ...TERISTICS RECEIVE SIDE 327 13 10AC CHARACTERISTICS BACKPLANE CLOCK TIMING 331 13 11AC CHARACTERISTICS TRANSMIT SIDE 332 13 12JTAG INTERFACE TIMING 335 14 JTAG INFORMATION 336 14 1 JTAG TAP CONTROLLER...

Page 6: ...igure 10 8 E1 Transmit Pulse Template 105 Figure 10 9 T1 Transmit Pulse Template 105 Figure 10 10 Jitter Tolerance 106 Figure 10 11 Jitter Tolerance E1 Mode 106 Figure 10 12 Jitter Attenuation T1 Mode...

Page 7: ...MII Interface Timing 316 Figure 13 3 Transmit RMII Interface Timing 317 Figure 13 4 Receive RMII Interface Timing 318 Figure 13 5 MDIO Interface Timing 319 Figure 13 6 Transmit WAN Interface Timing 3...

Page 8: ...e 10 14 Transmit Error Insertion Setup Sequence 111 Table 10 15 Error Insertion Examples 111 Table 11 1 Register Address Map 117 Table 11 2 Global Ethernet Mapper Register Bit Map 118 Table 11 3 Arbit...

Page 9: ...and T1 applications with the option of using a 1 544MHz MCLK in T1 applications and can be placed in either transmit or receive data paths An additional feature of the LIU is a CMI coder decoder for i...

Page 10: ...a Link FDL support is available through software only The TLINK RLINK TLCLK RLCLK pins are not available on the DS33R11 Multiplexed Microprocessor Bus mode is not supported on the DS33R11 The Extended...

Page 11: ...rupt driven environments Programmable FCS insertion and extraction Programmable FCS type Supports FCS error insertion Programmable packet size limits Minimum 64 bytes and maximum 2016 bytes Supports b...

Page 12: ...e Interface for 128Mb 32 bit wide SDRAM SDRAM Interface speed up to 100MHz Auto refresh timing Automatic precharge Master clock provided to the SDRAM No external components required for SDRAM connecti...

Page 13: ...eform generation T1 DSX 1 line build outs T1 CSU line build outs of 7 5dB 15dB and 22 5dB E1 waveforms include G 703 waveshapes for both 75 coax and 120 twisted cables AIS generation independent of lo...

Page 14: ...e signaling support o Software or hardware based o Interrupt generated on change of signaling data o Receive signaling freeze on loss of sync carrier loss or frame slip Addition of hardware pins to in...

Page 15: ...rns Daly pattern Error insertion single and continuous Total bit and errored bit counts Payload error insertion Error insertion in the payload portion of the T1 frame in the transmit path Errors can b...

Page 16: ...3 2002 CSMA CD access method and physical layer specifications RFC1662 PPP in HDLC like Framing RFC2615 PPP over SONET SDH X 86 Ethernet over LAPS RMII Industry Implementation Agreement for Reduced MI...

Page 17: ...r T1 E1 J1 T3 E3 OC 1 EC 1 G SHDSL or HDSL2 4 For an example of a complete LAN to WAN design refer to Application Note 3411 DS33Z11 Ethernet LAN to Unframed T1 E1 WAN Bridge available on our website a...

Page 18: ...ives from the Serial port is processed by the HDLC and stored in the SDRAM to be sent to the MAC transmitter Note 4 This data sheet assumes a particular nomenclature of the T1 operating environment In...

Page 19: ...waveshapes for driving the network and providing the correct source impedance depending on the type of media used T1 waveform generation includes DSX 1 line build outs as well as CSU line build outs o...

Page 20: ...LKO RSERO RSERI RCLKI RDEN TRANSMIT LIU RECEIVE LIU TRANSMIT FRAMER RECEIVIE FRAMER ETHERNET MAC P Port SDRAM PORT CST CS A0 A9 D0 D7 WR RD INT SDCS SRAS SCAS SWE SBA 0 1 SDATA 0 32 SDMASK 0 4 SDCLK J...

Page 21: ...OST INTERFACE T1 E1 J1 NETWORK CLOCK JTAG ESIB RX LIU JITTER ATTENUATOR LOCAL LOOPBACK REMOTE LOOPBACK FRAMER LOOPBACK PAYLOAD LOOPBACK MUX MUX EXTERNAL ACCESS TO RECEIVE SIGNALS EXTERNAL ACCESS TO TR...

Page 22: ...AL LOOPBACK TRING TTIP JITTER ATTENUATOR TRANSMIT OR RECEIVE PATH RECEIVE LINE I F RRING RTIP REMOTE LOOPBACK VCO PLL MCLK 8XCLK 32 768MHz XTALD RPOSO RNEGO RNEGI RPOSI TPOSI TNEGI TNEGO TPOSO RDCLKO...

Page 23: ...ANSMIT FRAMER DATA CLOCK SYNC SYNC CLOCK DATA FRAMER LOOPBACK XMIT HDLC 1 MAPPER XMIT HDLC 2 MAPPER 128 Byte FIFO 128 Byte FIFO MAPPER MAPPER REC HDLC 1 REC HDLC 2 128 Byte FIFO 128 Byte FIFO DATA CLO...

Page 24: ...ERO RCLKO RSYNC RDATA RFSYNC RMSYNC ELASTIC STORE SIGNALING BUFFER Sa BIT FDL EXTRACTION DATA CLOCK SYNC RCHBLK RCHCLK CHANNEL TIMING RSYSCLK TSERI TSIG TSSYNC TSYNC TDATA TESO TCHBLK TCHCLK TLINK TLC...

Page 25: ...9 Address bit 9 of the microprocessor interface D0 A14 IOZ Data Bit 0 Bidirectional data bit 0 of the microprocessor interface Least Significant Bit Not driven when CS 1 or RST 0 D1 B14 IOZ Data Bit 1...

Page 26: ...r Protocol Conversion Device This pin must be taken low for read write operations When CS is high the RD DS and WR signals are ignored CST D7 I Chip Select for the T1 E1 J1 Transceiver Must be low to...

Page 27: ...D 1 L19 RXD 2 L20 RXD 3 M18 O Receive Data 0 through 3 MII Four bits of received data sampled synchronously with the rising edge of RX_CLK For every clock cycle the PHY transfers 4 bits to the DS33R11...

Page 28: ...be up to 50MHz and should have 100ppm accuracy When in MII mode in DCE operation the DS33R11 uses this input to generate the RX_CLK and TX_CLK outputs as required for the Ethernet PHY interface When t...

Page 29: ...n for the PHY The user must leave this pin unconnected in the DCE Mode SDRAM INTERFACE SCAS W7 O SDRAM Column Address Strobe Active low output used to latch the column address on the rising edge of SD...

Page 30: ...ser programming for SDRAM buffering is required SDA 0 W14 SDA 1 W12 SDA 2 Y15 SDA 3 W15 SDA 4 Y14 SDA 5 V13 SDA 6 W13 SDA 7 Y12 SDA 8 V12 SDA 9 Y10 SDA 10 V14 SDA 11 W11 O SDRAM Address Bus 0 to 11 Th...

Page 31: ...programmable output that can be forced high or low during any of the channels Synchronous with TCLKT when the transmit side elastic store is disabled Synchronous with TSYSCLK when the transmit side e...

Page 32: ...ed by an external Serial to Parallel to convert TSERO stream to byte wide data This output indicates the last bit of the byte data sent serially on TSERO This signal is only active in the X 86 Mode T1...

Page 33: ...1 544MHz 2 048MHz 4 096MHz or 8 192MHz clock Only used when the receive side elastic store function is enabled Should be tied low in applications that do not use the receive side elastic store RFSYNC...

Page 34: ...the T1 E1 J1 Framer Clock used to clock data through the receive side framer This pin is normally connected to RDCLKO Can be internally connected to RDCLKO by connecting the LIUC pin high RDCLKO M3 O...

Page 35: ...nnected to TNEGI TPOSI B3 I Transmit Positive Data Input Sampled on the falling edge of TDCLKI for data to be transmitted out onto the T1 line Can be internally connected to TPOSO by connecting the LI...

Page 36: ...unction pin A zero to one transition issues a hardware reset to the transceiver register set A reset clears all configuration registers Configuration register contents are set to zero Leaving TSTRST h...

Page 37: ...384MHz 8 192MHz 4 096MHz or 2 048MHz When using the transceiver in T1 only operation a 1 544MHz 50ppm clock source can be used BPCLK B1 O Backplane Clock from T1 E1 J1 Transceiver A user selectable s...

Page 38: ...Pulling JTRST1 low restores normal device operation JTRST1 is pulled HIGH internally via a 10k resistor operation If boundary scan is not used this pin should be held low JTCLK2 A6 Ipu JTAG Clock 2 fo...

Page 39: ...onnect to the common supply ground DVDD D1 D17 E17 Digital Positive Supply Connect to 3 3V power supply DVSS N4 P4 R4 T4 Digital Signal Ground Connect to the common supply ground VDD1 8 B10 B15 C12 F3...

Page 40: ...3 QOVF TX_CLK VSS J RVSS RVSS RPOSI XTALD VDD3 VDD1 8 VSS VDD1 8 K RTIP RVSS RVDD 8XCLK VDD3 RX_ERR RX_DV VSS L RVDD RVSS RSIG RNEGI VDD3 RXD 0 RXD 1 RXD 2 M RRING RVSS RDCLKO RDCLKI VDD3 RXD 3 RX_CRS...

Page 41: ...erial port can operate with a gapped clock and is designed to be connected to the integrated T1 E1 J1 transceiver for transmission The DS33R11 can be configured through an 8 bit microprocessor interfa...

Page 42: ...With Intel timing selected the Read RD and Write WR pins are used to indicate read and write operations and latch data through the interface With Motorola timing selected the Read Write RW pin is use...

Page 43: ...rnet PHY In the DCE mode these are output pins and will output an internally generated clock to the Ethernet PHY The output clocks are generated by internal division of REF_CLK In RMII mode only the R...

Page 44: ...N JTCLK2 RDCLKI RDCLKO RSYSCLK RCHBLK RCHCLK RCLKO RCLKI RDEN TRANSMIT LIU RECEIVE LIU TRANSMIT FRAMER RECEIVIE FRAMER ETHERNET MAC P Port SDRAM PORT SDCLK JTCLK1 ARBITER CIR CONTROLLER PACKET HDLC X...

Page 45: ...due to the reset requirements in these operating modes In RMII mode receive and transmit timing is always synchronous to a 50 MHz clock input on the REF_CLK pin The source of REF_CLK is expected to b...

Page 46: ...the device Hardware JTAG Reset JTRST Pin Resets the JTAG test port Global Software Reset GL CR1 Writing to this bit resets the device Serial Interface Reset LI RSTPD Writing to this bit resets the Se...

Page 47: ...010Fh STEP 10 Setup connection in the GL CON1 register STEP 11 Configure the Serial Port register space as needed STEP 12 Configure the Ethernet Port register space as needed STEP 13 Configure the Et...

Page 48: ...of interrupt logic they must be enabled by placing a 1 in the associated bit location of the correct Interrupt Enable Register The Interrupt enable registers are LI TPPSRIE LI RPPSRIE LI RX86LSIE BSRI...

Page 49: ...qual to LI TRX86A 0 LI RX86S LI RX86LSIE Reserved 7 Reserved 6 Reserved 5 Reserved 4 Transmit Queue FIFO Overflowed 3 Transmit Queue Overflow 2 Transmit Queue for Connection Exceeded Low Threshold 1 T...

Page 50: ...wo groups condition bits and event bits Condition bits are typically network conditions such as loss of sync or all ones detect Event bits are typically markers such as the one second timer elastic st...

Page 51: ...Unidirectional connections are not supported When the user changes the queue sizes the connection must be torn down and re established When a connection is disconnected all transmit and receive queues...

Page 52: ...ce and the Serial Interface Note that once connection is set up then the queues and thresholds can be setup for that connection AR TQSC1 Size for the Transmit Queue in Number of 32 2K packets AR RQSC1...

Page 53: ...ATFLOW bit Note that the user does not have control over SU MACFCR FCE and FCB bits if ATFLOW is set The mechanism of sending pause or jam is dependent only on the receive queue high threshold Manual...

Page 54: ...reshold and a frame is received Pause is sent every time a frame is received in the high threshold state Pause control will only take care of temporary congestion Pause control does not take care of s...

Page 55: ...rrent frame that is being received during the watermark crossing but will wait to jam the next frame after the SU RQHT bit is set If the queue remains above the high threshold received frames will con...

Page 56: ...rame size is shown in Figure 9 4 The length includes only destination address source address VLAN tag 2 bytes type length field data and CRC32 The frame size is different than the 802 3 type length fi...

Page 57: ...was received The mode must be full duplex Unsupported control frame was received Note that frames received that are runt frames or frames with collision will automatically be rejected Table 9 5 Regist...

Page 58: ...connections for the DS33R11 in MII mode are shown in the following two figures In DCE Mode the DS33R11 transmitter is connected to an external receiver and DS33R11 receiver is connected to an external...

Page 59: ...CAWH A write command is issued by writing a zero to SU MACRWC MCRW and a one to SU MACRWC MCS MAC command status MCS is cleared by the DS33R11 when the operation is complete Reading from the MAC regis...

Page 60: ...AC MII MDIO Data Register Data to be written to or read from the PHY through MDIO interface 001Ch 001Fh SU MACFCR MAC Flow Control Register 0100h 0103h SU MMCCTRL MAC MMC Control Register Bit 0 for re...

Page 61: ...connections for MII operation are shown in Figure 9 5 and Figure 9 6 9 15 2 RMII Mode The Ethernet interface can be configured for RMII operation by setting the hardware pin RMIIMIIS high RMII interf...

Page 62: ...the Ethernet Mapper can be used for generation and detection of BERT patterns The BERT is a software programmable test pattern generator and monitor capable of meeting most error performance requireme...

Page 63: ...next 14 bits are all zeros QRSS is programmable on or off For PRBS and QRSS patterns the feedback is forced to one if bits 1 through 31 are all zeros Depending on the type of pattern programmed patte...

Page 64: ...Sync state Bit errors are determined by comparing the incoming data stream bit to the receive pattern generator output If they do not match a bit error is declared and the bit error and bit counts ar...

Page 65: ...x5 1 The polynomial used for FCS 32 is x32 x26 x23 x22 x16 x12 x11 x10 x8 x7 x5 x4 x2 x 1 The FCS is inverted after calculation The FCS type is programmable If FCS append is enabled the calculated FCS...

Page 66: ...discarded If packet processing is disabled inter frame fill filtering is not performed Packet abort detection searches for a packet abort sequence Between a packet start flag and a packet end flag if...

Page 67: ...e FIFO data RFD 7 0 DT 1 is the first bit received from the incoming data stream Once all of the packet processing has been completed The 8 bit parallel data stream is demultiplexed into a 32 bit para...

Page 68: ...DS33R11 expects a byte synchronization signal to provide the byte boundary for the X 86 receiver This is provided by the RBSYNC pin The functional timing is shown in Figure 12 4 The X 86 transmitter...

Page 69: ...capsulation on a complete serial stream if configured for X 86 mode in the register LI TX86E The DS33R11 provides the following functions Control Registers for Address Control SAPIH SAPIL 32 bit FCS e...

Page 70: ...er than 5d 5e 7e or dd is detected For the transmitter if X 86 is enabled the sequence of processing is as follows Construct frame including start flag SAPI Control and MAC frame Calculate FCS Perform...

Page 71: ...e the interface will request the data if there is a positive credit balance If the credit balance is negative transmit interface does not request data New credit balance is calculated credit balance o...

Page 72: ...nd clarity Figure 10 1 T1 E1 J1 Clock Map The TCLKT MUX is dependent on the state of the TCSS0 and TCSS1 bits in the TR CCR1 register and the state of the TCLKT pin TRANSMIT FORMATTER RECEIVE FRAMER B...

Page 73: ...found in the TR PCPR register 10 3 T1 E1 J1 Transceiver Interrupts Various alarms conditions and events in the T1 E1 J1 transceiver can cause interrupts For simplicity these are all referred to as ev...

Page 74: ...T1 channels have bit 7 stuffing performed on them regardless of how the TR SSIEx registers are programmed In this manner the TR SSIEx registers are only affecting the channels that are to have robbed...

Page 75: ...e channels is set to 0 for at least 254 occurrences When bit 2 of 256 consecutive channels is set to 0 for fewer than 254 occurrences D4 12th F Bit Mode TR T1RCR2 0 1 this mode is also referred to as...

Page 76: ...d TR E1TCR2 There are also four status and information registers Each of these eight registers is described in this section Table 10 3 E1 Sync Resync Criteria FRAME OR MULTIFRAME LEVEL SYNC CRITERIA R...

Page 77: ...ble 10 4 E1 Alarm Criteria ALARM SET CRITERIA CLEAR CRITERIA ITU SPECIFICATION RLOS An RLOS condition exists on power up prior to initial synchronization when a resync criteria has been met or when a...

Page 78: ...RLOS 1 conditions Table 10 5 shows what the LCVCRs count Table 10 5 T1 Line Code Violation Counting Options COUNT EXCESSIVE ZEROS TR ERCNT 0 B8ZS ENABLED TR T1RCR2 5 COUNTED IN THE LCVCRs No No BPVs...

Page 79: ...f synchronization RLOS 1 conditions Table 10 7 shows what errors the TR PCVCR counts Table 10 7 T1 Path Code Violation Counting Arrangements FRAMING MODE COUNT Fs ERRORS COUNTED IN THE PCVCRs D4 No Er...

Page 80: ...attern ESF MOS Number of multiframes out of sync ESF F Bit Errors in the FPS pattern In E1 mode TR FOSCR counts word errors in the FAS in time slot 0 This counter is disabled when RLOS is high FAS err...

Page 81: ...S0 channel pointed to by the TCM0 to TCM4 bits appear in the transmit DS0 monitor TR TDS0M register The DS0 channel pointed to by the RCM0 to RCM4 bits appear in the receive DS0 TR RDS0M register The...

Page 82: ...rame boundaries This function is always enabled 10 9 1 1 Change of State To avoid constant monitoring of the receive signaling registers the transceiver can be programmed to alert the host when any sp...

Page 83: ...enabled however the backplane clock can be either 1 544MHz or 2 048MHz Signaling reinsertion can be enabled on a per channel basis by setting the RSRCS bit high in the TR PCPR register The channels t...

Page 84: ...s the robbed bit signaling T1 or TS16 CAS signaling E1 for two time slots that are inserted into the outgoing stream if enabled to do so through TR T1TCR1 4 T1 mode or TR E1TCR1 6 E1 mode In T1 mode o...

Page 85: ...12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Phone Channel 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 10 9 4 Hardware Based Transmit Signaling...

Page 86: ...codes first select a channel by writing to the TR IAAR register Then write the idle code to the TR PCICR register For successive writes there is no need to load the TR IAAR with the next consecutive...

Page 87: ...de substitution for transmit channels 2 through 8 Although an idle code was programmed for channel 1 by the block write function above enabling it for channel 1 would step on the frame alignment alarm...

Page 88: ...a 1 544MHz or 2 048MHz clock at the RSYSCLK pin The user has the option of either providing a frame multiframe sync at the RSYNC pin or having the RSYNC pin provide a pulse on frame multiframe boundar...

Page 89: ...eful primarily in synchronous applications RSYSCLK TSYSCLK are locked to RCLKO TCLKT respectively Table 10 11 Table 10 11 Elastic Store Delay After Initialization INITIALIZATION REGISTER BIT DELAY Rec...

Page 90: ...nt is used to modify the CRC 4 checksum This modification however does not corrupt any error information the original CRC 4 checksum may contain In this mode of operation TSYNC must be configured to m...

Page 91: ...eive BOC The receive BOC function is enabled by setting TR BOCC 4 1 The TR RFDL register now operates as the receive BOC message and information register The lower six bits of the TR RFDL register BOC...

Page 92: ...rs are only being used to source the align frame and nonalign frame sync patterns then the host need only write once to these registers Data in the Si bit position is overwritten if either the framer...

Page 93: ...to a singular controller The HDLC controller performs the entire necessary overhead for generating and receiving performance report messages PRMs as described in ANSI T1 403 and the messages as descr...

Page 94: ...lable Indicates the number of bytes that can be read from the receive FIFO TR H1TFBA HDLC 1 Transmit FIFO Buffer Available TR H2TFBA HDLC 2 Transmit FIFO Buffer Available Indicates the number of bytes...

Page 95: ...e FIFO s write pointer is above the watermark If enabled this condition can also cause an interrupt through the INT pin 10 16 3 HDLC Mapping The HDLC controllers must be assigned a space in the T1 E1...

Page 96: ...tailed message status If the value in the TR HxRPBA register refers to the beginning portion of a message or continuation of a message then the MSB of the TR HxRPBA register returns a value of 1 This...

Page 97: ...ther of the bytes programmed into the TR RFDLM1 or TR RFDLM2 registers then the TR SR8 1 bit is set to a 1 and the INT pin toggles low if enabled through TR IMR8 1 This feature allows an external micr...

Page 98: ...of an LAPD protocol The LAPD protocol states that no more than five 1s should be transmitted in a row so that the data does not resemble an opening or closing flag 01111110 or an abort signal 11111111...

Page 99: ...loop up and loop down code detection The user programs the codes to be detected in the receive up code definition TR RUPCD1 and TR RUPCD2 registers and the receive down code definition TR RDNCD1 and...

Page 100: ...ugh a coupling transformer The line driver can handle both CEPT 30 ISDN PRI lines for E1 and long haul CSU or short haul DSX 1 lines for T1 10 20 2 Receiver The receiver contains a digital clock recov...

Page 101: ...main below the programmed threshold for approximately 50ms for this bit to be set The accuracy of the receive level indication is 1 LSB 2 5dB from 25 C to 85 C and 2 LSBs 5dB from 40 C to 25 C 10 20 2...

Page 102: ...atic gain In the fixed gain mode the transmitter outputs a fixed current into the network load to achieve a nominal pulse amplitude In the automatic gain mode the transmitter adjusts its output level...

Page 103: ...block or the clock applied at the TCLKT pin to create a smooth jitter free clock that is used to clock data out of the jitter attenuator FIFO It is acceptable to provide a gapped bursty clock at the...

Page 104: ...RS R SHOULD BE SET TO 60 EACH IF THE INTERNAL RECEIVE SIDE TERMINATION FEATURE IS ENABLED WHEN THIS FEATURE IS DISABLED R 37 5 FOR 75 COAXIAL E1 LINES 60 FOR 120 TWISTED PAIR E1 LINES OR 50 FOR 100 TW...

Page 105: ...it Pulse Template 0 0 1 0 2 0 3 0 4 0 5 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 0 1 1 1 2 500 300 100 0 300 500 700 400 200 200 400 600 100 TIME ns NORMALIZED AMPLITUDE T1 102 87 T1 403 CB 119 OCT 79 AN...

Page 106: ...QUENCY Hz UNIT INTERVALS UI P P 1k 100 10 1 0 1 10 100 1k 10k 100k DEVICE TOLERANCE 1 TR 62411 DEC 90 ITU T G 823 Figure 10 11 Jitter Tolerance E1 Mode FREQUENCY Hz UNIT INTERVALS UI P P 1k 100 10 1 0...

Page 107: ...Mode FREQUENCY Hz 0dB 20dB 40dB 60dB 1 10 100 1K 10K JITTER ATTENUATION dB 100K TR 62411 Dec 90 Prohibited Area C u r v e B C u r v e A T1 MODE Figure 10 13 Jitter Attenuation E1 Mode FREQUENCY Hz 0 2...

Page 108: ...re must read the BERT information register BIR to determine which event s has occurred To activate the BERT block the host must configure the BERT mux through the TR BIC register 10 25 1 BERT Status T...

Page 109: ...ERT RECEIVER 1 0 FROM RECEIVE FRAMER TO RECEIVE SYSTEM BACKPLANE INTERFACE FROM TRANSMIT SYSTEM BACKPLANE INTERFACE TO TRANSMIT FRAMER Figure 10 16 Simplified Diagram of BERT in Backplane Direction BE...

Page 110: ...ser would place 00h in TR BRP1 00h in TR BRP2 7Eh in TR BRP3 and 7Eh in TR BRP4 and the alternating word counter would be set to 50 decimal to allow 100 bytes of 00h followed by 100 bytes of 7Eh to be...

Page 111: ...ate in the TR ERC register Note If TR ER3 through TR ER0 0 no errors are generated even if the constant error insertion feature is enabled 2A or 2B For constant error insertion set CE 1 TR ERC 4 For a...

Page 112: ...nnections into a USART or LAPD controller in fractional T1 E1 or ISDN PRI applications The receive and transmit paths have independent enables Channel formats supported include 56kbps and 64kbps This...

Page 113: ...GRAM KEY PIN SELECTOR REGISTER Hardware Signaling Estore Mux Payload Loopback HDLC Mux 1 HDLC Mux 2 HDLC FDL 2 HDLC FDL 1 TDATA TESO TLINK H1TC 4 THMS1 FDL Mux TFDL Tx FDL Zero Stuffer H2TC 4 THMS2 T1...

Page 114: ...TFM T1CCR1 2 TYEL T1TCR1 0 CRC Mux TCPT T1TCR1 5 D4 bit 2 Yellow Alm BERT Engine BERT Mux F bit Corruption Payload error insertion TFM T1CCR1 2 TD4YM T1TCR2 2 TYEL T1TCR1 0 TFUS BIC 3 F bit BTCS1 3 fr...

Page 115: ...S1 H1TC 4 H1TCS1 4 H1TTSBS T1SaBE4 T1SaBE8 THMS1 H1TC 4 H1TTSBS 4 H1TTSBS 0 HDLC Engine 2 THMS2 H2TC 4 H2TCS1 4 H2TTSBS T2SaBE4 T2SaBE8 THMS2 H2TC 4 H2TTSBS 4 H2TTSBS 0 BTCS1 4 BERTEN BIC 0 from PCPR...

Page 116: ...to AIS Gen UA1 Gen E1TCR2 1 AAIS E1TCR1 5 TUA1 HDB3 Encoding E1TCR1 2 THDB3 To Bipolar NRZ coding Mux E1 TRANSMIT FLOW DIAGRAM TFPT E1TCR1 7 TDS0SEL 0 TDS0SEL 4 116 of 344 Per Channel Loopback From Id...

Page 117: ...ports The registers associated with the MAC must be configured through indirect register write read access due to the architecture of the device When writing to a register input values for unused bits...

Page 118: ...egister Bit Map ADDR Name BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 00h GL IDRL ID07 ID06 ID05 ID04 ID03 ID02 ID01 ID00 01h GL IDRH ID15 ID14 ID13 ID12 ID11 ID10 ID09 ID08 02h GL CR1 REF_CLKO IN...

Page 119: ...BSP0 085h BSPB1R BSP15 BSP14 BSP13 BSP12 BSP11 BSP10 BSP9 BSP8 086h BSPB2R BSP23 BSP22 BSP21 BSP20 BSP19 BSP18 BSP17 BSP16 087h BSPB3R BSP31 BSP30 BSP29 BSP28 BSP27 BSP26 BSP25 BSP24 088h TEICR TIER2...

Page 120: ...X86TRA6 X86TRA5 X86TRA4 X86TRA3 X86TRA2 X86TRA1 X86TRA0 0DAh LI TRX8C X86TRC7 X86TRC6 X86TRC5 X86TRC4 X86TRC3 X86TRC2 X86TRC1 X86TRC0 0DBh LI TRX86SAPIH TRSAPIH7 TRSAPIH6 TRSAPIH5 TRSAPIH4 TRSAPIH3 T...

Page 121: ...Bh LI RBC3 RBC31 RBC30 RBC29 RBC28 RBC27 RBC26 RBC25 RBC24 11Ch LI RAC0 REBC7 REBC6 REBC5 REBC4 REBC3 REBC2 REBC1 REBC0 11Dh LI RAC1 REBC15 REBC14 REBC13 REBC12 REBC11 REBC10 REBC9 REBC8 11Eh LI RAC2...

Page 122: ...D21 MACWD20 MACWD19 MACWD18 MACWD17 MACWD16 149h SU MACWD3 MACD31 MACD30 MACD29 MACD28 MACD27 MACD26 MACD25 MACD24 14Ah SU MACAWL MACAW 7 MACAW 6 MACAW 5 MACAW4 MACAW3 MACAW2 MACAW1 MACAW0 14Bh SU MAC...

Page 123: ...rved Reserved Reserved Reserved 0013h Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0014h SU MACMIIA 31 24 Reserved Reserved Reserved Reserved Reserved Reserved Rese...

Page 124: ...TEC29 TXBYTEC28 TXBYTEC27 TXBYTEC26 TXBYTEC25 TXBYTEC24 309h 23 16 TXBYTEC23 TXBYTEC22 TXBYTEC21 TXBYTEC20 TXBYTEC19 TXBYTEC18 TXBYTEC17 TXBYTEC16 30Ah 15 8 TXBYTEC15 TXBYTEC14 TXBYTEC13 TXBYTEC12 TXB...

Page 125: ...H1 CH1 UCAW 009 h TR SSIE2 T1 TR SSIE2 E1 CH16 CH15 CH15 CH14 CH14 CH13 CH13 CH12 CH12 CH11 CH11 CH10 CH10 CH9 CH9 CH8 00A h TR SSIE3 T1 TR SSIE3 E1 CH24 CH22 CH23 CH21 CH22 CH20 CH21 CH19 CH20 CH18 C...

Page 126: ...WM TNF 024 h TR SR8 BOCC RFDLAD RFDLF TFDLE RMTCH RBOC 025 h TR IMR8 BOCC RFDLAD RFDLF TFDLE RMTCH RBOC 026 h TR SR9 BBED BBCO BEC0 BRA1 BRA0 BRLOS BSYNC 027 h TR IMR9 BBED BBCO BEC0 BRA1 BRA0 BRLOS B...

Page 127: ...CH26 CH25 040 h TR SIGCR GRSRE RFE RFF RCCS TCCS FRSAO 041 h TR ERCNT MECU ECUS EAMS VCRFS FSBE MOSCRF LCVCRF 042 h TR LCVCR1 LCVC15 LCVC14 LCVC13 LCVC12 LCVC11 LCVC10 LCVC9 LCCV8 043 h TR LCVCR2 LCV...

Page 128: ...it Signaling Bit Format Changes With Operating Mode See Register Definition 05C h TR TS13 Transmit Signaling Bit Format Changes With Operating Mode See Register Definition 05D h TR TS14 Transmit Signa...

Page 129: ...ODM TCSS1 TCSS0 RLOSF 071 h TR CCR2 BPCS1 BPCS0 BPEN 072 h TR CCR3 TDATFMT TGPCKEN RDATFMT RGPCKEN 073 h TR CCR4 RLT3 RLT2 RLT1 RLT0 UOP3 UOP2 UOP1 UOP0 074 h TR TDS0SEL TCM4 TCM3 TCM2 TCM1 TCM0 075 h...

Page 130: ...H1FC TFLWM2 TFLWM1 TFLWM0 RFHWM2 RFHWM1 RFHWM0 092 h TR H1RCS1 RHCS8 RHCS7 RHCS6 RHCS5 RHCS4 RHCS3 RHCS2 RHCS1 093 h TR H1RCS2 RHCS16 RHCS15 RHCS14 RHCS13 RHCS12 RHCS11 RHCS10 RHCS9 094 h TR H1RCS3 RH...

Page 131: ...9 0A9 h TR H2TCS3 THCS24 THCS23 THCS22 THCS21 THCS20 THCS19 THCS18 THCS17 0AA h TR H2TCS4 THCS32 THCS31 THCS30 THCS29 THCS28 THCS27 THCS26 THCS25 0AB h TR H2TTSBS TCB8SE TCB7SE TCB6SE TCB5SE TCB4SE TC...

Page 132: ...0CD h TR RSa6 RSa6F1 RSa6F3 RSa6F5 RSa6F7 RSa6F9 RSa6F11 RSa6F13 RSa6F15 0CE h TR RSa7 RSa7F1 RSa7F3 RSa7F5 RSa7F7 RSa7F9 RSa7F11 RSa7F13 RSa7F15 0CF h TR RSa8 RSa8F1 RSa8F3 RSa8F5 RSa8F7 RSa8F9 RSa8...

Page 133: ...h TR BC2 EIB2 EIB1 EIB0 SBE RPL3 RPL2 RPL1 RPL0 0E2 h Reserved 0E3 h TR BBC1 BBC7 BBC6 BBC5 BBC4 BBC3 BBC2 BBC1 BBC0 0E4 h TR BBC2 BBC15 BBC14 BBC13 BBC12 BBC11 BBC10 BBC9 BBC8 0E5 h TR BBC3 BBC23 BB...

Page 134: ...Bit 4 ID04 If this bit is set the device contains a MII interface Bit 3 ID03 If this bit is set the device contains an Ethernet PHY Bits 0 2 ID00 ID02 A three bit count that is equal to 000b for the f...

Page 135: ...bit is set to 1 all of the internal data path and status and control registers except this RST bit on all ports are reset to their default state This bit must be set high for a minimum of 100ns 0 Norm...

Page 136: ...n read Register Name GL SRCALS Register Description Global SDRAM Reference Clock Activity Latched Status Register Address 05h Bit 7 6 5 4 3 2 1 0 Name REFCLKS SYSCLS Default Bit 1 Reference Clock Acti...

Page 137: ...ceive has an enabled interrupt generating event Serial Interface interrupts consist of HDLC interrupts and X 86 interrupts Register Name GL SIE Register Description Global Ethernet Interface Interrupt...

Page 138: ...errupt Status Register Address 0Bh Bit 7 6 5 4 3 2 1 0 Name TQ1IS RQ1IS Default 0 0 0 0 0 0 0 0 Bit 4 Transmit Queue 1 Interrupt Enable TQ1IS If this bit is set to 1 the Transmit Queue 1 has interrupt...

Page 139: ...5 4 3 2 1 0 Name LINE1 0 Default 0 0 0 0 0 0 0 1 Bit 0 LINE1 0 This bit is preserved to provide software compatibility with multiport devices The LINE1 0 bit selects the Ethernet port that is to be c...

Page 140: ...e subsequent reset operations Bit 1 HDLC Read Pointer Reset C1MHPR Setting this bit to 1 resets the transmit queue read pointer for connection 1 This queue pointer must be reset after a disconnect and...

Page 141: ...This bit is valid only after the BIST test is complete and the BIST DN bit is set If set this bit can only be cleared by resetting the DS33R11 Register Name GL SDMODE1 Register Description Global SDRA...

Page 142: ...3Ch Bit 7 6 5 4 3 2 1 0 Name SDMW Default 0 0 0 0 0 0 0 0 Bit 0 SDRAM Mode Write SDMW Setting this bit to 1 will write the current values of the mode control and refresh time control registers to the...

Page 143: ...queue is for data arriving from the MAC to be sent to the WAN The Queue address size is defined in increments of 32 x 2048 bytes The queue size is AR RQSC1 multiplied by 32 to determine the number of...

Page 144: ...eive incoming data stream is not altered When 1 the receive incoming data stream is inverted Bit 3 Manual Pattern Resynchronization MPR A zero to one transition of this bit will cause the receive patt...

Page 145: ...n generator is forced to one if the next fourteen output bits are all zero Bit 5 Pattern Type Select PTS When 0 the pattern is a PRBS pattern When 1 the pattern is a repetitive pattern Register Name B...

Page 146: ...ion BERT Pattern Byte2 Register Register Address 86h Bit 7 6 5 4 3 2 1 0 Name BSP23 BSP22 BSP21 BSP20 BSP19 BSP18 BSP17 BSP16 Default 0 0 0 0 0 0 0 0 Bits 0 to 7 BERT Pattern BSP 23 16 8 bits of 32 bi...

Page 147: ...ingle Error Insert TSEI This bit causes a bit error to be inserted in the transmit data stream if and single bit error insertion is enabled A 0 to 1 transition causes a single bit error to be inserted...

Page 148: ...S bit changes state Register Name BSRIE Register Description BERT Status Register Interrupt Enable Register Address 90h Bit 7 6 5 4 3 2 1 0 Name PMSIE BEIE BECIE OOSIE Default 0 0 0 0 0 0 0 0 Bit 3 Pe...

Page 149: ...egister description below Register Name RBECR2 Register Description Receive Bit Error Count Byte 2 Register Register Address 96h Bit 7 6 5 4 3 2 1 0 Name BEC23 BEC22 BEC21 BEC20 BEC19 BEC18 BEC17 BEC1...

Page 150: ...4 3 2 1 0 Name BC23 BC22 BC21 BC20 BC19 BC18 BC17 BC16 Default 0 0 0 0 0 0 0 0 Bits 0 7 Bit Count BC 16 23 Eight bits of a 32 bit value Register description below Register Name RBCB3 Register Descript...

Page 151: ...he associated event occurs and remains set until it is cleared by reading Once cleared a latched bit will not be set again until the associated event occurs again Reserved configuration bits and regis...

Page 152: ...ch packet When equal to 0 the calculated FCS bytes are appended to packets When set to 1 packets are transmitted without FCS In X 86 Mode FCS is always 32 bits and is always appended to the packet Bit...

Page 153: ...least the value of TIFG 7 0 plus 1 Note If inter frame fill is set to all 1 s a TFIG value of 2 or 3 will result in a flag two bytes of 1 s and an additional flag between packets Register Name LI TEPL...

Page 154: ...the value y which has a maximum value of 6 If TPER 3 0 has a value of 0h errored packet insertion is disabled If TPER 6 4 has a value of 6xh or 7xh the errored packet rate is x 106 A TPER 6 0 value o...

Page 155: ...ion process is initiated Register Name LI TPPSRL Register Description Transmit Packet Processor Status Register Latched Register Address 0C9h Bit 7 6 5 4 3 2 1 0 Name TEPFL Default Bit 0 Transmit Erro...

Page 156: ...nsmit Packet Count Byte 1 Register Address 0CDh Bit 7 6 5 4 3 2 1 0 Name TPC15 TPC14 TPC13 TPC12 TPC11 TPC10 TPC9 TPC8 Default 0 0 0 0 0 0 0 0 Bits 0 7 Transmit Packet Count TPC 15 8 Eight bits of 24...

Page 157: ...ster Description Transmit Byte Count Byte 2 Register Address 0D2h Bit 7 6 5 4 3 2 1 0 Name TBC23 TBC22 TBC21 TBC20 TBC19 TBC18 TBC17 TBC16 Default 0 0 0 0 0 0 0 0 Bits 0 7 Transmit Byte Count TBC 23 1...

Page 158: ...g registers counters to be updated A 0 to 1 transition causes the performance monitoring registers to be updated with the latest data and the counters reset 0 or 1 This update updates performance moni...

Page 159: ...e X 86 Address Register Address 0D9h Bit 7 6 5 4 3 2 1 0 Name X86TRA7 X86TRA6 X86TRA5 X86TRA4 X86TRA3 X86TRA2 X86TRA1 X86TRA0 Default 0 0 0 0 0 1 0 0 Bits 0 7 X86 Transmit Receive Address X86TRA0 7 Th...

Page 160: ...R3 CIR2 CIR1 CIR0 Default 0 0 0 0 0 0 0 1 Bit 7 Committed Information Rate Enable CIRE Set this bit to 1 to enable the Committed Information Rate Controller feature Bits 0 6 Committed Information Rate...

Page 161: ...appended to packets When set to 1 FCS processing is disabled the packets do not have an FCS appended In X 86 mode FCS processing is always enabled Bit 4 Receive FCS 16 Enable RF16 When 0 the error che...

Page 162: ...ximum packet size is less than the minimum packet size all packets are discarded When packet processing is disabled these sixteen bits indicate the packet size the incoming data is to be broken into T...

Page 163: ...bit is set when a packet with a noninteger number of bytes is detected Bit 4 Receive Small Packet Detected Latched RSPDL This bit is set when a packet smaller than the minimum packet size is detected...

Page 164: ...disabled 1 interrupt enabled Bit 4 Receive Small Packet Detected Interrupt Enable RSPDIE This bit enables an interrupt if the RSPDL bit in the LI RPPSRL register is set 0 interrupt disabled 1 interrup...

Page 165: ...1 0 Name RPC15 RPC14 RPC13 RPC12 RPC11 RPC10 RPC09 RPC08 Default 0 0 0 0 0 0 0 0 Bits 0 7 Receive Packet Count RPC 15 8 Eight bits of a 24 bit value Register description below Register Name LI RPCB2...

Page 166: ...gister Register Address 10Dh Bit 7 6 5 4 3 2 1 0 Name RFPC15 RFPC14 RFPC13 RFPC12 RFPC11 RFPC10 RFPC9 RFPC8 Default 0 0 0 0 0 0 0 0 Bits 0 7 Receive FCS Errored Packet Count RFPC 15 8 Eight bits of a...

Page 167: ...h Bit 7 6 5 4 3 2 1 0 Name RAPC15 RAPC14 RAPC13 RAPC12 RAPC11 RAPC10 RAPC9 RAPC8 Default 0 0 0 0 0 0 0 0 Bits 0 7 Receive Aborted Packet Count RAPC 15 8 Eight bits of a 24 bit value Register descripti...

Page 168: ...3 2 1 0 Name RSPC15 RSPC14 RSPC13 RSPC12 RSPC11 RSPC10 RSPC9 RSPC8 Default 0 0 0 0 0 0 0 0 Bits 0 7 Receive Size Violation Packet Count RSPC 15 8 Eight bits of a 24 bit value Register description bel...

Page 169: ...alue Register description below Register Name LI RBC2 Register Description Receive Byte Count 2 Register Register Address 11Ah Bit 7 6 5 4 3 2 1 0 Name RBC23 RBC22 RBC21 RBC20 RBC19 RBC18 RBC17 RBC16...

Page 170: ...value Register description below Register Name LI RAC2 Register Description Receive Aborted Byte Count 2 Register Register Address 11Eh Bit 7 6 5 4 3 2 1 0 Name REBC23 REBC22 REBC21 REBC20 REBC19 REBC...

Page 171: ...PMU Update Status RPMUUS This bit is set when the Transmit PMU Update is completed This bit is cleared when RPMUU is set to 0 Register Name LI RX86S Register Description Receive X 86 Latched Status Re...

Page 172: ...Register Address 124h Bit 7 6 5 4 3 2 1 0 Name TQLT7 TQLT6 TQLT5 TQLT4 TQLT3 TQLT2 TQLT1 TQLT0 Default 0 0 0 0 0 0 0 0 Bits 0 7 Transmit Queue Low Threshold TQLT 0 7 The transmit queue low threshold f...

Page 173: ...the watermark interrupt is enabled for TQLTS Register Name LI TQCTLS Register Description Serial Interface Transmit Queue Cross Threshold Latched Status Register Address 127h Bit 7 6 5 4 3 2 1 0 Name...

Page 174: ...2 1 0 Name MACRA7 MACRA6 MACRA5 MACRA4 MACRA3 MACRA2 MACRA1 MACRA0 Default 0 0 0 0 0 0 0 0 Bits 0 7 MAC Read Address MACRA0 7 Low byte of the MAC indirect register address Used only for read operatio...

Page 175: ...RD16 23 One of four bytes of data read from the MAC Valid after a read command has been issued and the SU MACRWC MCS bit is zero Register Name SU MACRD3 Register Description MAC Read Data byte 3 Regis...

Page 176: ...its 0 7 MAC Write Data 2 MACWD16 23 One of four bytes of data to be written to the MAC Data has been written after a write command has been issued and the SU MACRWC MCS bit is zero Register Name SU MA...

Page 177: ...0 0 0 0 0 0 0 0 Bit 1 MAC Command RW MCRW If this bit is written to 1 a read is performed from the MAC If this bit is written to 0 a write operation is performed Address information for write operatio...

Page 178: ...ket size supported by the Ethernet interface is still 2016 this includes the 4 bytes of CRC Bit 2 H10S This bit controls the 10 100 selection for RMII and DCE Mode When in RMII mode setting this bit t...

Page 179: ...nsmitted immediately instead of being deferred If this bit is set to 0 the frame is deferred if CRS is asserted and sent when the CRS is unasserted indicating the media is idle Bit 1 Transmit Packet H...

Page 180: ...d frames Valid only in half duplex operation Bit 2 No Carrier NOC When this bit is set to 1 a frame was aborted because no carrier was found for transmission Bit 1 Reserved Bit 0 Frame Abort FABORT Wh...

Page 181: ...are the upper bits of the length in bytes of the received frame with FCS and Padding If Automatic Pad Stripping is enabled this value is the length of the received packet without PCS or Pad bytes Regi...

Page 182: ...t 3 Multicast Frame MCF This bit is set to 1 if the current frame is a multicast frame Bit 2 Unsupported Control Frame UF This bit is set to 1 if the frame received is a control frame with an opcode t...

Page 183: ...ve unpredictable behavior and should be avoided Register Name SU RQLT Register Description Receive Queue Low Threshold Watermark Register Address 15Ah Bit 7 6 5 4 3 2 1 0 Name RQLT7 RQLT6 RQLT5 RQLT4...

Page 184: ...ter Name SU QCRLS Register Description Queue Cross Threshold Latched Status Register Address 15Dh Bit 7 6 5 4 3 2 1 0 Name RFOVFLS RQOVFLS RQHTLS RQLTLS Default Bit 3 Receive FIFO Overflow latched Sta...

Page 185: ...ngth field and actual number of bytes received are allowed When equal to zero only frames with matching length fields and actual bytes received will be allowed Bit 3 CRC Error Reject CRCERR When set t...

Page 186: ...6 05 04 03 02 01 00 Name BOLMT1 BOLMT0 DC Reserved TE RE Reserved Reserved Default 0 0 0 0 0 0 0 0 Bit 28 Heartbeat Disable HDB When set to 1 the heartbeat SQE function is disabled This bit should be...

Page 187: ...y for collided packets Default operation limits the maximum delay for retransmission to a countdown of 10 bits from a random number generator The user can reduce the maximum number of counter bits as...

Page 188: ...1 00 Name MIIA1 MIIA0 Reserved Reserved Reserved Reserved MIIW MIIB Default 1 1 0 0 0 0 0 0 Bits 11 15 PHY Address PHYA 0 4 These 5 bits select one of the 32 available PHY address locations to access...

Page 189: ...019h Bit 23 22 21 20 19 18 17 16 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Default 0 0 0 0 0 0 0 0 001Ah Bit 15 14 13 12 11 10 09 08 Name MIID15 MIID14 MIID13 MIID12...

Page 190: ...Reserved Reserved Reserved Reserved FCE FCB Default 0 0 0 0 0 0 1 0 Bits 16 31 Pause Time PT 00 15 These bits are used for the Pause Time Field in transmitted Pause Frames This value is the number of...

Page 191: ...Reserved Reserved Reserved Reserved Reserved Reserved Default 0 0 0 0 0 0 0 0 0102h Bit 15 14 13 12 11 10 09 08 Name Reserved Reserved MXFRM10 MXFRM9 MXFRM8 MXFRM7 MXFRM6 MXFRM5 Default 0 0 1 0 1 1 1...

Page 192: ...10Dh Bit 23 22 21 20 19 18 17 16 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Default 0 0 0 0 0 0 0 0 010Eh Bit 15 14 13 12 11 10 09 08 Name Reserved Reserved Reserved...

Page 193: ...111h Bit 23 22 21 20 19 18 17 16 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Default 0 0 0 0 0 0 0 0 0112h Bit 15 14 13 12 11 10 09 08 Name Reserved Reserved Reserved...

Page 194: ...ault 0 0 0 0 0 0 0 0 0203h Bit 07 06 05 04 03 02 01 00 Name RXFRMC7 RXFRMC6 RXFRMC5 RXFRMC4 RXFRMC3 RXFRMC2 RXFRMC1 RXFRMC0 Default 0 0 0 0 0 0 0 0 Bits 0 31 All Frames Received Counter RXFRMC 0 31 32...

Page 195: ...0 0 0 0 0 0 0207h Bit 07 06 05 04 03 02 01 00 Name RXFRMOK7 RXFRMOK6 RXFRMOK5 RXFRMOK4 RXFRMOK3 RXFRMOK2 RXFRMOK1 RXFRMOK0 Default 0 0 0 0 0 0 0 0 Bits 0 31 Frames Received OK Counter RXFRMOK 0 31 32...

Page 196: ...t 0 0 0 0 0 0 0 0 0303h Bit 07 06 05 04 03 02 01 00 Name TXFRMC7 TXFRMC6 TXFRMC5 TXFRMC4 TXFRMC3 TXFRMC2 TXFRMC1 TXFRMC0 Default 0 0 0 0 0 0 0 0 Bits 0 31 All Frames Transmitted Counter TXFRMC 0 31 32...

Page 197: ...EC8 Default 0 0 0 0 0 0 0 0 030Bh Bit 07 06 05 04 03 02 01 00 Name TXBYTEC7 TXBYTEC6 TXBYTEC5 TXBYTEC4 TXBYTEC3 TXBYTEC2 TXBYTEC1 TXBYTEC0 Default 0 0 0 0 0 0 0 0 Bits 0 31 All Bytes Transmitted Count...

Page 198: ...ult 0 0 0 0 0 0 0 0 030Fh Bit 07 06 05 04 03 02 01 00 Name TXBYTEOK7 TXBYTEOK6 TXBYTEOK5 TXBYTEOK4 TXBYTEOK3 TXBYTEOK2 TXBYTEOK1 TXBYTEOK0 Default 0 0 0 0 0 0 0 0 Bits 0 31 Bytes Transmitted OK Counte...

Page 199: ...Bit 07 06 05 04 03 02 01 00 Name TXFRMU7 TXFRMU6 TXFRMU5 TXFRMU4 TXFRMU3 TXFRMU2 TXFRMU1 TXFRMU0 Default 0 0 0 0 0 0 0 0 Bits 0 31 Frames Aborted Due to FIFO Under Run Counter TXFRMU 0 31 32 bit valu...

Page 200: ...ult 0 0 0 0 0 0 0 0 033Bh Bit 07 06 05 04 03 02 01 00 Name TXFRMBD7 TXFRMBD6 TXFRMBD5 TXFRMBD4 TXFRMBD3 TXFRMBD2 TXFRMBD1 TXFRMBD0 Default 0 0 0 0 0 0 0 0 Bits 0 to 31 All Frames Aborted Counter TXFRM...

Page 201: ...On Output Pins 0 0 Operate normally 0 1 Force all output pins into tri state including all I O pins and parallel port pins 1 0 Force all output pins low including all I O pins except parallel port pi...

Page 202: ...iframe mode TR IOCR1 5 1 TR IOCR1 4 0 0 RSYNC outputs CAS multiframe boundaries 1 RSYNC outputs CRC4 multiframe boundaries Bit 5 RSYNC Mode Select 1 RSMS1 Selects frame or multiframe pulse when RSYNC...

Page 203: ...0 no inversion 1 inverts signal on RCLKO output Bit 6 TCLKT Invert TCLKINV 0 no inversion 1 inverts signal on TCLKT input Bit 5 RSYNC Invert RSYNCINV 0 no inversion 1 invert Bit 4 TSYNC Invert TSYNCIN...

Page 204: ...frame bits in error 0 1 2 5 frame bits in error 1 0 2 6 frame bits in error 1 1 2 6 frame bits in error Bit 3 Sync Criteria SYNCC In D4 Framing Mode 0 search for Ft pattern then search for Fs pattern...

Page 205: ...SLC 96 framing applications See Section 10 18 for details 0 SLC 96 disabled 1 SLC 96 enabled Bit 3 Receive FDL Zero Destuffer Enable RZSE Set this bit to 0 if using the internal HDLC BOC controller i...

Page 206: ...TSSE 0 do not source signaling data from the TR TSx registers regardless of the TR SSIEx registers The TR SSIEx registers still define which channels are to have B7 stuffing preformed 1 source signali...

Page 207: ...et this bit to 0 if using the internal HDLC controller instead of the legacy support for the FDL See Section 15 for details 0 zero stuffer disabled 1 zero stuffer enabled Bit 4 F Bit Corruption Type 2...

Page 208: ...8 x N 1 bits where N 1 through 23 Violations for the transmit and receive data streams are reported in the TR INFO1 6 and TR INFO1 7 bits respectively When this bit is set to 1 the T1 E1 J1 transceive...

Page 209: ...TS1 register Register Name TR SSIE2 T1 Mode Register Description Software Signaling Insertion Enable 2 Register Address 09h Bit 7 6 5 4 3 2 1 0 Name CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9 Default 0 0...

Page 210: ...s 16 to 22 CH16 to CH22 These bits determine which channels are to have signaling inserted from the transmit signaling registers 0 do not source signaling data from the TR TSx registers for this chann...

Page 211: ...Register 2 Register Address 0Dh Bit 7 6 5 4 3 2 1 0 Name CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9 Default 0 0 0 0 0 0 0 0 Bits 0 7 Receive Digital Milliwatt Enable for Channels 9 to 16 CH9 to CH16 0 do...

Page 212: ...ts for pulse density Bit 6 Transmit Pulse Density Violation Event TPDV Set when the transmit data stream does not meet the ANSI T1 403 requirements for pulse density Bit 5 Change of Frame Alignment Ev...

Page 213: ...ing detected Bit 5 Transmit Current Limit Exceeded TCLE A real time bit that is set when the 50mA RMS current limiter is activated whether the current limiter is enabled or not Bit 4 Transmit Open Cir...

Page 214: ...or The FASRC will go active indicating a search for a valid FAS has been activated Bit 0 CAS Resync Criteria Met Event CASRC Set when two consecutive CAS MF alignment words are received in error Regis...

Page 215: ...Change of State Event RSCOS Set when any channel selected by the receive signaling change of state interrupt enable registers TR RSCSE1 through TR RSCSE4 changes signaling state Bit 4 Jitter Attenuato...

Page 216: ...d 1 interrupt enabled Bit 4 Jitter Attenuator Limit Trip Event JALT 0 interrupt masked 1 interrupt enabled Bit 3 Line Interface Receive Carrier Loss Condition LRCL 0 interrupt masked 1 interrupt enabl...

Page 217: ...Event FRCLC Set when the carrier loss condition at RPOSI and RNEGI is no longer detected Bit 4 Receive Loss of Sync Clear Event RLOSC Set when the framer achieves synchronization remains set until rea...

Page 218: ...Framer Receive Carrier Loss Condition Clear FRCLC 0 interrupt masked 1 interrupt enabled Bit 4 Receive Loss of Sync Clear Event RLOSC 0 interrupt masked 1 interrupt enabled Bit 3 Receive Yellow Alarm...

Page 219: ...eived See Section 10 19 for details This is a double interrupt bit See Section 9 7 Bit 4 Loss of Transmit Clock Condition LOTC Set when the TCLKT pin has not transitioned for one channel time Forces t...

Page 220: ...ode Detected Condition LUP 0 interrupt masked 1 interrupt enabled interrupts on rising and falling edges Bit 4 Loss of Transmit Clock Condition LOTC 0 interrupt masked 1 interrupt enabled interrupts o...

Page 221: ...ransmit multiframe boundaries Used to alert the host that signaling data needs to be updated T1 Mode Set every 1 5ms on D4 MF boundaries or every 3ms on ESF MF boundaries Bit 3 Transmit Align Frame Ev...

Page 222: ...ve Signaling All Ones Event RSAO 0 interrupt masked 1 interrupt enabled Bit 5 Receive Signaling All Zeros Event RSAZ 0 interrupt masked 1 interrupt enabled Bit 4 Transmit Multiframe Event TMF 0 interr...

Page 223: ...y Event TESEM Set when the transmit elastic store buffer empties and a frame is repeated Bit 3 Transmit Elastic Store Slip Occurrence Event TSLIP Set when the transmit elastic store has either repeate...

Page 224: ...SF 0 interrupt masked 1 interrupt enabled Bit 4 Transmit Elastic Store Empty Event TESEM 0 interrupt masked 1 interrupt enabled Bit 3 Transmit Elastic Store Slip Occurrence Event TSLIP 0 interrupt mas...

Page 225: ...king error or an overrun condition or an abort has been seen This is a latched bit and is cleared when read Bit 4 Receive Packet Start Event RPS Set when the HDLC controller detects an opening byte Th...

Page 226: ...vent RPE 0 interrupt masked 1 interrupt enabled Bit 4 Receive Packet Start Event RPS 0 interrupt masked 1 interrupt enabled Bit 3 Receive FIFO Above High Watermark Condition RHWM 0 interrupt masked 1...

Page 227: ...preceded by a corrupt CRC codeword 0 1 1 Abort Packet ended because an abort signal was detected seven or more 1s in a row 1 0 0 Overrun HDLC controller terminated reception of packet because receive...

Page 228: ...egister matches TR RFDLM1 or TR RFDLM2 Bit 0 Receive BOC Detector Change of State Event RBOC Set whenever the BOC detector sees a change of state to a valid BOC The setting of this bit prompts the use...

Page 229: ...Cleared when read and is not set again until another overflow occurs Bit 3 BERT Receive All Ones Condition BRA1 A latched bit that is set when 32 consecutive 1s are received Allowed to be cleared onc...

Page 230: ...terrupt enabled Bit 4 BERT Error Counter Overflow Event BECO 0 interrupt masked 1 interrupt enabled Bit 3 Receive All Ones Condition BRA1 0 interrupt masked 1 interrupt enabled interrupts on rising an...

Page 231: ...ceive Signaling Reinsertion Channel Select RSRCS Bit 5 Receive Fractional Channel Select RFCS Bit 4 Bert Receive Channel Select BRCS Bit 3 Transmit Hardware Signaling Channel Select THSCS Bit 2 Payloa...

Page 232: ...4 CH13 CH12 CH11 CH10 CH9 Register Name TR PCDR3 Register Description Per Channel Data Register 3 Register Address 2Bh Bit 7 6 5 4 3 2 1 0 Name Default CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17 Register...

Page 233: ...hing for alignment at the FAS level This is a read only non latched real time bit It is not necessary to precede the read of this bit with a write Bit 1 CAS MF Sync Active CASSA Set while the synchron...

Page 234: ...e slot 26 1 force RCHBLK high during bit 1 of time slot 26 Bit 3 Receive CRC4 Enable RCRC4 0 CRC4 disabled 1 CRC4 enabled Bit 2 Frame Resync Criteria FRC 0 resync if FAS received in error three consec...

Page 235: ...n the TR PCPR register 1 source time slot 16 from TR TS1 to TR TS16 registers Bit 5 Transmit Unframed All Ones TUA1 0 transmit data normally 1 transmit an unframed all ones code at TPOSO and TNEGO Bit...

Page 236: ...BR RBF1 RBF0 SBOC Default 0 0 0 0 0 0 0 0 Bit 4 Receive BOC Enable RBOCE Enables the receive BOC function The TR RFDL register reports the received BOC code and two information bits when this bit is s...

Page 237: ...bit in registers TR RSINFO1 4 is set An interrupt is generated if the channel was also enabled as an interrupt source by setting the appropriate bit in TR RSCSE1 4 The bit remains set until read Regi...

Page 238: ...eceive side signaling at RSIG and RSERO if receive signaling reinsertion is enabled overrides receive freeze enable RFE See Section 10 9 2 3 for details 0 do not force a freeze event 1 force a freeze...

Page 239: ...counters once a second 1 update error counters every 42ms 333 frames E1 Mode 0 update error counters once a second 1 update error counters every 62 5ms 500 frames Bit 4 Error Accumulation Mode Select...

Page 240: ...0 0 0 0 0 0 0 Bits 0 7 Line Code Violation Counter Bits 0 to 7 LCVC0 to LCVC7 LCVC0 is the LSB of the 16 bit code violation count Register Name TR PCVCR1 Register Description Path Code Violation Coun...

Page 241: ...0 Name FOS7 FOS6 FOS5 FOS4 FOS3 FOS2 FOS1 FOS0 Default 0 0 0 0 0 0 0 0 Bits 0 7 Frames Out of Sync Counter Bits 0 to 7 FOS0 to FOS7 FOS0 is the LSB of the 16 bit frames out of sync count Register Name...

Page 242: ...e 6 2 for more details Bit 1 Payload Loopback PLB When set to 1 payload loopback is enabled and the following occurs 1 Data is transmitted from the TPOSO and TNEGO pins synchronous with RCLKO instead...

Page 243: ...Enable for Channels 9 to 16 CH9 to CH16 0 loopback disabled 1 enable loopback source data from the corresponding receive channel Register Name TR PCLR3 Register Description Per Channel Loopback Enable...

Page 244: ...lastic Store Minimum Delay Mode TESMDM See Section 10 12 4 for details 0 elastic stores operate at full two frame depth 1 elastic stores operate at 32 bit depth Bit 4 Transmit Elastic Store Enable TES...

Page 245: ...CH10 C CH10 D CH9 A CH9 B CH9 C CH9 D TS6 CH12 A CH12 B CH12 C CH12 D CH11 A CH11 B CH11 C CH11 D TS7 CH14 A CH14 B CH14 C CH14 D CH13 A CH13 B CH13 C CH13 D TS8 CH16 A CH16 B CH16 C CH16 D CH15 A CH...

Page 246: ...14 15 16 TS2 17 18 19 20 21 22 23 24 TS3 25 26 27 28 29 30 31 32 TS4 33 34 35 36 37 38 39 40 TS5 41 42 43 44 45 46 47 48 TS6 49 50 51 52 53 54 55 56 TS7 57 58 59 60 61 62 63 64 TS8 65 66 67 68 69 70...

Page 247: ...CH5 C CH5 D TS3 CH8 A CH8 B CH8 C CH8 D CH7 A CH7 B CH7 C CH7 D TS4 CH10 A CH10 B CH10 C CH10 D CH9 A CH9 B CH9 C CH9 D TS5 CH12 A CH12 B CH12 C CH12 D CH11 A CH11 B CH11 C CH11 D TS6 CH14 A CH14 B C...

Page 248: ...A CH7 B TS4 CH10 A CH10 B CH10 A CH10 B CH9 A CH9 B CH9 A CH9 B TS5 CH12 A CH12 B CH12 A CH12 B CH11 A CH11 B CH11 A CH11 B TS6 CH14 A CH14 B CH14 A CH14 B CH13 A CH13 B CH13 A CH13 B TS7 CH16 A CH16...

Page 249: ...CH21 C CH21 D RS11 CH24 A CH24 B CH24 C CH24 D CH23 A CH23 B CH23 C CH23 D RS12 Register Name TR RS1 to TR RS12 Register Description Receive Signaling Registers T1 Mode D4 Format Register Address 60h...

Page 250: ...H20 D CH19 A CH19 B CH19 C CH19 D RS11 CH22 A CH22 B CH22 C CH22 D CH21 A CH21 B CH21 C CH21 D RS12 CH24 A CH24 B CH24 C CH24 D CH23 A CH23 B CH23 C CH23 D RS13 CH26 A CH26 B CH26 C CH26 D CH25 A CH25...

Page 251: ...O and TNEGO are one full TCLKO period wide 1 pulses at TPOSO and TNEGO are one half TCLKO period wide Bit 3 Disable Idle Code Auto Increment DICAI Selects deselects the auto increment feature for the...

Page 252: ...t hardware signaling is enabled 0 elastic store is source of multiframe sync 1 framer or TSYNC pin is source of multiframe sync Bit 6 Interrupt Disable INTDIS This bit is convenient for disabling inte...

Page 253: ...0 0 0 1 2 5 0 0 1 0 5 0 0 0 1 1 7 5 0 1 0 0 10 0 0 1 0 1 12 5 0 1 1 0 15 0 0 1 1 1 17 5 1 0 0 0 20 0 1 0 0 1 22 5 1 0 1 0 25 0 1 0 1 1 27 5 1 1 0 0 30 0 1 1 0 1 32 5 1 1 1 0 35 0 1 1 1 1 Less than 37...

Page 254: ...r Description Receive Channel Monitor Select Register Address 76h Bit 7 6 5 4 3 2 1 0 Name RCM4 RCM3 RCM2 RCM1 RCM0 Default 0 0 0 0 0 0 0 0 Bits 0 4 Receive Channel Monitor Bits RCM0 to RCM4 RCM0 is t...

Page 255: ...1 6 TT0 and TT1 of LIC4 register must be set to 0 in this configuration T1 Mode L2 L1 L0 Application N 1 Return Loss Rt 1 0 0 0 DSX 1 0ft to 133ft 0dB CSU 1 2 NM 0 0 0 1 DSX 1 133ft to 266ft 1 2 NM 0...

Page 256: ...ontrol the gain setting for the nonautomatic gain mode Use the tables below for setting the recommended values The LB line build out column refers to the value in the L0 L2 bits in TR LIC1 Line Interf...

Page 257: ...TUA1 The polarity of this bit is set such that the device transmits an all ones pattern on power up or device reset This bit must be set to a 1 to allow the device to transmit data The transmission of...

Page 258: ...of RDCLKO 1 update RPOSO and RNEGO on falling edge of RDCLKO Bits 3 4 Monitor Mode MM0 to MM1 MM1 MM0 Internal Linear Gain Boost dB 0 0 Normal operation no boost 0 1 20 1 0 26 1 1 32 Bit 2 Receive Sy...

Page 259: ...0 6 176 1 0 0 12 352 1 1 0 2 048 0 0 1 4 096 0 1 1 8 192 1 0 1 16 384 1 1 1 E1 Mode MCLK MHz MPS1 MPS0 JAMUX TR LIC2 3 2 048 0 0 0 4 096 0 1 0 8 192 1 0 0 16 384 1 1 0 Bits 2 3 Transmit Termination Se...

Page 260: ...1 Updates all transmit channels 1 0 Updates all receive channels 1 1 Updates all transmit and receive channels Bits 0 5 Channel Pointer Address Bits IAA0 to IAA5 These bits select the channel to be pr...

Page 261: ...do not insert data from the idle code array into the transmit data stream 1 insert data from the idle code array into the transmit data stream Register Name TR TCICE4 Register Description Transmit Cha...

Page 262: ...s CH17 to CH24 0 do not insert data from the idle code array into the receive data stream 1 insert data from the idle code array into the receive data stream Register Name TR RCICE4 Register Descripti...

Page 263: ...el Blocking Register 3 Register Address 8Ah Bit 7 6 5 4 3 2 1 0 Name CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17 Default 0 0 0 0 0 0 0 0 Bits 0 7 Receive Channels 17 to 24 Channel Blocking Control Bits CH...

Page 264: ...s CH9 to CH16 0 force the TCHBLK pin to remain low during this channel time 1 force the TCHBLK pin high during this channel time Register Name TR TCBR3 Register Description Transmit Channel Blocking R...

Page 265: ...nd flushes the transmit FIFO An abort followed by 7Eh or FFh flags idle is transmitted until a new packet is initiated by writing new data into the FIFO Must be cleared and set again for a subsequent...

Page 266: ...WM1 TFLWM0 RFHWM2 RFHWM1 RFHWM0 Default 0 0 0 0 0 0 0 0 Bits 3 5 Transmit FIFO Low Watermark Select TFLWM0 to TFLWM2 TFLWM2 TFLWM1 TFLWM0 Transmit FIFO Watermark bytes 0 0 0 4 0 0 1 16 0 1 0 32 0 1 1...

Page 267: ...7 Receive HDLC Channel Select Bit 7 RHCS7 Select Channel 8 16 24 or 32 Bit 6 Receive HDLC Channel Select Bit 6 RHCS6 Select Channel 7 15 23 or 31 Bit 5 Receive HDLC Channel Select Bit 5 RHCS5 Select...

Page 268: ...e RCB7SE Set to 1 to stop this bit from being used Bit 5 Receive Channel Bit 6 Suppress Enable RCB6SE Set to 1 to stop this bit from being used Bit 4 Receive Channel Bit 5 Suppress Enable Sa4 Bit Enab...

Page 269: ...Transmit HDLC Channel Select Bit 7 THCS7 Select Channel 8 16 24 or 32 Bit 6 Transmit HDLC Channel Select Bit 6 THCS6 Select Channel 7 15 23 or 31 Bit 5 Transmit HDLC Channel Select Bit 5 THCS5 Select...

Page 270: ...TCB1SE Set to 1 to stop this bit from being used Bit 2 Transmit Channel Bit 3 Suppress Enable Sa6 Bit Enable TCB1SE Set to 1 to stop this bit from being used Bit 1 Transmit Channel Bit 2 Suppress Enab...

Page 271: ...Bit 2 Transmit HDLC Data Bit 2 THD2 Bit 1 Transmit HDLC Data Bit 1 THD1 Bit 0 Transmit HDLC Data Bit 0 THD0 LSB of an HDLC packet data byte Register Name TR H1RF TR H2RF Register Description HDLC 1 R...

Page 272: ...BCC Register Description In Band Code Control Register Register Address B6h Bit 7 6 5 4 3 2 1 0 Name TC1 TC0 RUP2 RUP1 RUP0 RDN2 RDN1 RDN0 Default 0 0 0 0 0 0 0 0 Bits 6 7 Transmit Code Length Definit...

Page 273: ...2 Transmit Code Definition Bit 2 C2 A don t care if a 5 bit length is selected Bit 1 Transmit Code Definition Bit 1 C1 A don t care if a 5 bit or 6 bit length is selected Bit 0 Transmit Code Definiti...

Page 274: ...is selected Bit 4 Receive Up Code Definition Bit 4 C4 A don t care if a 1 bit to 3 bit length is selected Bit 3 Receive Up Code Definition Bit 3 C3 A don t care if a 1 bit to 4 bit length is selected...

Page 275: ...selected Bit 4 Receive Down Code Definition Bit 4 C4 A don t care if a 1 bit to 3 bit length is selected Bit 3 Receive Down Code Definition Bit 3 C3 A don t care if a 1 bit to 4 bit length is selected...

Page 276: ...Spare Control Register Register Address BDh Bit 7 6 5 4 3 2 1 0 Name RSC2 RSC1 RSC0 Default 0 0 0 0 0 0 0 0 Bits 3 7 Unused must be set to 0 for proper operation Bits 0 2 Receive Spare Code Length De...

Page 277: ...lected Bit 4 Receive Spare Code Definition Bit 4 C4 A don t care if a 1 bit to 3 bit length is selected Bit 3 Receive Spare Code Definition Bit 3 C3 A don t care if a 1 bit to 4 bit length is selected...

Page 278: ...BOC Bit 0 RBOC0 Register Name TR RFDL TR BOCC 4 0 Register Description Receive FDL Register Register Address C0h Bit 7 6 5 4 3 2 1 0 Name RFDL7 RFDL6 RFDL5 RFDL4 RFDL3 RFDL2 RFDL1 RFDL0 Default 0 0 0...

Page 279: ...DL Bit 5 TFDL5 Bit 4 Transmit FDL Bit 4 TFDL4 Bit 3 Transmit FDL Bit 3 TFDL3 Bit 2 Transmit FDL Bit 2 TFDL2 Bit 1 Transmit FDL Bit 1 TFDL1 Bit 0 Transmit FDL Bit 0 TFDL0 LSB of the transmit FDL code R...

Page 280: ...t Signal Bit 1 Bit 3 Frame Alignment Signal Bit 1 Bit 2 Frame Alignment Signal Bit 0 Bit 1 Frame Alignment Signal Bit 1 Bit 0 Frame Alignment Signal Bit 1 Register Name TR RNAF Register Description Re...

Page 281: ...rame 6 SiF6 Bit 3 Si Bit of Frame 8 SiF8 Bit 2 Si Bit of Frame 10 SiF10 Bit 1 Si Bit of Frame 12 SiF12 Bit 0 Si Bit of Frame 14 SiF14 Register Name TR RSiNAF Register Description Received Si Bits of t...

Page 282: ...Bit 3 Remote Alarm Bit of Frame 9 RRAF9 Bit 2 Remote Alarm Bit of Frame 11 RRAF11 Bit 1 Remote Alarm Bit of Frame 13 RRAF13 Bit 0 Remote Alarm Bit of Frame 15 RRAF15 Register Name TR RSa4 Register Des...

Page 283: ...7 Bit 3 Sa5 Bit of Frame 9 RSa5F9 Bit 2 Sa5 Bit of Frame 11 RSa5F11 Bit 1 Sa5 Bit of Frame 13 RSa5F13 Bit 0 Sa5 Bit of Frame 15 RSa5F15 Register Name TR RSa6 Register Description Received Sa6 Bits Reg...

Page 284: ...7 Bit 3 Sa7 Bit of Frame 9 RSa7F9 Bit 2 Sa7 Bit of Frame 11 RSa7F11 Bit 1 Sa7 Bit of Frame 13 RSa7F13 Bit 0 Sa7 Bit of Frame 15 RSa7F15 Register Name TR RSa8 Register Description Received Sa8 Bits Reg...

Page 285: ...Bit 3 Frame Alignment Signal Bit 1 Bit 2 Frame Alignment Signal Bit 0 Bit 1 Frame Alignment Signal Bit 1 Bit 0 Frame Alignment Signal Bit 1 Register Name TR TNAF Register Description Transmit Nonalig...

Page 286: ...6 TSiF6 Bit 3 Si Bit of Frame 8 TSiF8 Bit 2 Si Bit of Frame 10 TSiF10 Bit 1 Si Bit of Frame 12 TSiF12 Bit 0 Si Bit of Frame 14 TSiF14 Register Name TR TSiNAF Register Description Transmit Si Bits of t...

Page 287: ...Bit 3 Remote Alarm Bit of Frame 9 TRAF9 Bit 2 Remote Alarm Bit of Frame 11 TRAF11 Bit 1 Remote Alarm Bit of Frame 13 TRAF13 Bit 0 Remote Alarm Bit of Frame 15 TRAF15 Register Name TR TSa4 Register Des...

Page 288: ...5F7 Bit 3 Sa5 Bit of Frame 9 TSa5F9 Bit 2 Sa5 Bit of Frame 11 TSa5F11 Bit 1 Sa5 Bit of Frame 13 TSa5F13 Bit 0 Sa5 Bit of Frame 15 TSa5F15 Register Name TR TSa6 Register Description Transmit Sa6 Bits R...

Page 289: ...7 Bit 3 Sa7 Bit of Frame 9 TSa7F9 Bit 2 Sa7 Bit of Frame 11 TSa7F11 Bit 1 Sa7 Bit of Frame 13 TSa7F13 Bit 0 Sa7 Bit of Frame 15 TSa7F15 Register Name TR TSa8 Register Description Transmit Sa8 Bits Reg...

Page 290: ...data stream 1 insert data from the TR TSa4 register into the transmit data stream Bit 3 Additional Bit 5 Insertion Control Bit Sa5 0 do not insert data from the TR TSa5 register into the transmit dat...

Page 291: ...AT13 RPAT12 RPAT11 RPAT10 RPAT9 RPAT8 Default 0 0 0 0 0 0 0 0 Bits 0 7 BERT Repetitive Pattern Set Bits 8 to 15 RPAT8 to RPAT15 Register Name TR BRP3 Register Description BERT Repetitive Pattern Set R...

Page 292: ...ttern QRSS A 220 1 pattern with 14 consecutive zero restrictions 1 0 0 Repetitive pattern 1 0 1 Alternating word pattern 1 1 0 Modified 55 octet Daly pattern The Daly pattern is a repeating 55 octet p...

Page 293: ...creates a single bit error Must be cleared and set again for a subsequent bit error to be inserted Bits 0 3 Repetitive Pattern Length Bit 3 RPL0 to RPL3 RPL0 is the LSB and RPL3 is the MSB of a nibble...

Page 294: ...Name BBC15 BBC14 BBC13 BBC12 BBC11 BBC10 BBC9 BBC8 Default 0 0 0 0 0 0 0 0 Bits 0 7 BERT Bit Counter Bits 8 to 15 BBC8 to BBC15 Register Name TR BBC3 Register Description BERT Bit Count Register 3 Reg...

Page 295: ...e 24 bit counter Register Name TR BEC2 Register Description BERT Error Count Register 2 Register Address E8h Bit 7 6 5 4 3 2 1 0 Name EC15 EC14 EC13 EC12 EC11 EC10 EC9 EC8 Default 0 0 0 0 0 0 0 0 Bits...

Page 296: ...byte align its pattern with the transmit formatter This bit must be transitioned in order to byte align the Daly pattern Bit 3 Transmit Framed Unframed Select TFUS 0 BERT does not source data into the...

Page 297: ...ock cycle Subsequent updates require that the WNOE bit be set to 0 and then 1 once again Bit 4 Constant Errors CE When this bit is set high and the ER0 to ER3 bits are not set to 0000 the error insert...

Page 298: ...e C7 C6 C5 C4 C3 C2 C1 C0 Default 0 0 0 0 0 0 0 0 Bits 0 7 Number of Errors Counter Bits 0 to 7 C0 to C7 Bit C0 is the LSB of the 10 bit counter Register Name TR NOE2 Register Description Number of Er...

Page 299: ...umber of Errors Left 1 Register Address EEh Bit 7 6 5 4 3 2 1 0 Name C7 C6 C5 C4 C3 C2 C1 C0 Default 0 0 0 0 0 0 0 0 Bits 0 7 Number of Errors Left Counter Bits 0 to 7 C0 to C7 Bit C0 is the LSB of th...

Page 300: ...ough LI TSLCR In the figure below TDEN is active low allowing the bits to clock and inactive high causing the next data bit not be clocked TCLKE can be gapped as shown in the following figure Similarl...

Page 301: ...ts the RBSYNC byte indicator as shown in Figure 12 4 Figure 12 3 Transmit Byte Sync Functional Timing last bit 1st bit TCLKE TBYSYNC TSERO Figure 12 4 Receive Byte Sync Functional Timing last bit 1st...

Page 302: ...TX_EN TX_CLK P R E A M B L E J J J J J J J J CRS COL Receive Data RXD 3 0 is clocked from the external PHY synchronously with RX_CLK The RX_CLK signal is 2 5MHz for 10Mbit s operation and 25MHz for 10...

Page 303: ...7 8 9 10 11 12 1 2 3 4 5 3 RSYNC 1 RSYNC RFSYNC 2 RSYNC NOTE 1 RSYNC IN THE FRAME MODE TR IOCR1 5 0 AND DOUBLE WIDE FRAME SYNC IS NOT ENABLED TR IOCR1 6 0 NOTE 2 RSYNC IN THE FRAME MODE TR IOCR1 5 0...

Page 304: ...C A D B LSB F MSB MSB LSB A B NOTE 1 RCHBLK IS PROGRAMMED TO BLOCK CHANNEL 24 Figure 12 13 Receive Side 1 544MHz Boundary Timing Elastic Store Enabled RSERO CHANNEL 23 CHANNEL 24 CHANNEL 1 RCHCLK RCH...

Page 305: ...RSYNC IS IN THE OUTPUT MODE TR IOCR1 4 0 NOTE 3 RSYNC IS IN THE INPUT MODE TR IOCR1 4 1 NOTE 4 RCHBLK IS FORCED TO 1 IN THE SAME CHANNELS AS RSERO SEE NOTE 1 NOTE 5 THE F BIT POSITION IS PASSED THROU...

Page 306: ...R IOCR1 3 0 NOTE 2 TSYNC IN FRAME MODE TR IOCR1 2 0 AND DOUBLE WIDE FRAME SYNC IS ENABLED TR IOCR1 3 1 NOTE 3 TSYNC IN MULTIFRAME MODE TR IOCR1 2 1 Figure 12 17 Transmit Side Boundary Timing with Elas...

Page 307: ...d LSB F LSB MSB CHANNEL 1 CHANNEL 32 A B C A D B A B C A D B TSYSCLK TSERI TSSYNC TSIG TCHCLK TCHBLK CHANNEL 31 A CHANNEL 31 CHANNEL 32 CHANNEL 1 1 4 2 3 NOTE 1 TSERI DATA IN CHANNELS 1 5 9 13 17 21 2...

Page 308: ...5 1 NOTE 3 THIS DIAGRAM ASSUMES THE CAS MF BEGINS IN THE RAF FRAME Figure 12 21 Receive Side Boundary Timing with Elastic Store Disabled CHANNEL 32 CHANNEL 1 CHANNEL 2 CHANNEL 32 CHANNEL 1 CHANNEL 2...

Page 309: ...S ADDED FORCED TO ON 1 NOTE 2 RSYNC IN THE OUTPUT MODE TR IOCR1 4 0 NOTE 3 RSYNC IN THE INPUT MODE TR IOCR1 4 1 NOTE 4 RCHBLK IS PROGRAMMED TO BLOCK CHANNEL 24 Figure 12 23 Receive Side Boundary Timin...

Page 310: ...SCLK TCLKT TSYSCLK RSERO TSERI RCHCLK TCHCLK RCHBLK TCHBLK 1 2 0 NOTE RCHBLK OR TCHBLK PROGRAMMED TO PULSE HIGH DURING TIME SLOTS 1 THROUGH 15 17 THROUGH 25 AND BIT 1 OF TIME SLOT 26 Figure 12 25 Tran...

Page 311: ...SYNC IS IN THE INPUT MODE TR IOCR1 1 0 NOTE 3 TCHBLK IS PROGRAMMED TO BLOCK CHANNEL 2 NOTE 5 THE SIGNALING DATA AT TSIG DURING CHANNEL 1 IS NORMALLY OVERWRITTEN IN THE TRANSMIT FORMATTER WITH THE CAS...

Page 312: ...Figure 12 28 Transmit Side Boundary Timing TSYSCLK 2 048MHz Elastic Store Enabled LSB F LSB MSB CHANNEL 1 CHANNEL 32 A B C D A B TSYSCLK TSERI TSSYNC TSIG TCHCLK TCHBLK CHANNEL 31 A CHANNEL 31 CHANNE...

Page 313: ...a convection cooled JEDEC test enclosure Note The typ values listed below are not production tested Table 13 1 Recommended DC Operating Conditions VDD3 3 3 3V 5 VDD1 8 1 8V 5 Tj 40 C to 85 C PARAMETER...

Page 314: ...for 256 Pin 27mm BGA Notes 2 3 20 3 C W Note 1 The package is mounted on a four layer JEDEC standard test board Note 2 Value guaranteed by design GBD Note 3 Theta JA JA is the junction to ambient ther...

Page 315: ...bps 100Mbps PARAMETER SYMBOL MIN TYP MAX MIN TYP MAX UNITS TX_CLK Period t1 400 40 ns TX_CLK Low Time t2 140 260 14 26 ns TX_CLK High Time t3 140 260 14 26 ns TX_CLK to TXD TX_EN Delay t4 0 20 0 20 ns...

Page 316: ...TYP MAX MIN TYP MAX UNITS RX_CLK Period t5 400 40 ns RX_CLK Low Time t6 140 260 14 26 ns RX_CLK High Time t7 140 260 14 26 ns RXD RX_DV to RX_CLK Setup Time t8 5 5 ns RX_CLK to RXD RX_DV Hold Time t9...

Page 317: ...TER SYMBOL MIN TYP MAX MIN TYP MAX UNITS REF_CLK Frequency 50MHz 50ppm 50MHz 50ppm REF_CLK Period t1 20 20 ns REF_CLK Low Time t2 7 13 7 13 ns REF_CLK High Time t3 7 13 7 13 ns REF_CLK to TXD TX_EN De...

Page 318: ...ITS REF_CLK Frequency 50MHz 50ppm 50MHz 50ppm MHz REF_CLK Period t1 20 20 ns REF_CLK Low Time t2 7 13 7 13 ns REF_CLK High Time t3 7 13 7 13 ns RXD CRS_DV to REF_CLK Setup Time t8 5 5 ns REF_CLK to RX...

Page 319: ...IN TYP MAX UNITS MDC Frequency 1 67 MHz MDC Period t1 540 600 660 ns MDC Low Time t2 270 300 330 ns MDC High Time t3 270 300 330 ns MDC to MDIO Output Delay t4 20 10 ns MDIO Setup Time t5 10 ns MDIO H...

Page 320: ...TCLKE Frequency 52 MHz TCLKE Period t1 19 2 ns TCLKE Low Time t2 8 ns TCLKE High Time t3 8 ns TCLKE to TSERO Output Delay t4 3 10 ns TCLKE to TBSYNC Setup Time t5 3 5 ns TBSYNC Hold Time t6 7 ns TCLK...

Page 321: ...ns RCLKI Low Time t2 8 ns RCLKI High Time t3 8 ns RSERI Setup Time t4 7 ns RDEN Setup Time t4 7 ns RBSYNC Setup Time t4 7 ns RDEN Setup Time t4 7 ns RBSYNC Setup Time t4 7 ns RSERI Hold Time t5 2 ns R...

Page 322: ...ns SDCLKO to SDATA Drive Off Write to SDRAM t6 4 ns SDATA to SDCLKO Setup Time Read from SDRAM t7 2 ns SDCLKO to SDATA Hold Time Read from SDRAM t8 2 ns SDCLKO to SRAS SCAS SWE SDCS Active Read or Wri...

Page 323: ...with Integrated T1 E1 J1 Transceiver 323 of 344 Figure 13 8 SDRAM Interface Timing SDCLKO output SDATA output t1 SDATA input SRAS SCAS SWE SDCS output t2 t3 t5 t6 t7 t8 t10 t9 SDA SBA output SDMASK ou...

Page 324: ...s Setup Time for CS Active to Either RD or WR Active t2 0 ns Delay Time from either RD or DS Active to DATA 7 0 Valid t3 75 ns Hold Time from either RD or WR Inactive to CS Inactive t4 0 ns Hold Time...

Page 325: ...sceiver 325 of 344 Figure 13 9 Intel Bus Read Timing MODEC 00 t2 t3 Address Valid Data Valid t4 t9 t5 t10 ADDR 12 0 DATA 7 0 CS RD WR t1 Figure 13 10 Intel Bus Write Timing MODEC 00 t2 t6 Address Vali...

Page 326: ...er 326 of 344 Figure 13 11 Motorola Bus Read Timing MODEC 01 t2 t3 Address Valid Data Valid t4 t9 t5 t10 ADDR 12 0 DATA 7 0 DS RW t1 CS CST Figure 13 12 Motorola Bus Write Timing MODEC 01 t2 t6 Addres...

Page 327: ...tSP Note 5 488 ns tSH 20 0 5 tSP ns RSYSCLK Pulse Width tSL 20 0 5 tSP ns RSYNC Setup to RSYSCLK Falling tSU 20 ns RSYNC Pulse Width tPW 50 ns RPOSI RNEGI Setup to RDCLKI Falling tSU 20 ns RPOSI RNEGI...

Page 328: ...eiver 328 of 344 Figure 13 13 Receive Side Timing tD1 1 tD2 RSERO RDATA RSIG RCHCLK RCHBLK RSYNC RCLKO RFSYNC RMSYNC tD2 tD2 tD2 1ST FRAME BIT NOTE 1 RSYNC IS IN THE OUTPUT MODE NOTE 2 NO RELATIONSHIP...

Page 329: ...eceive Side Timing Elastic Store Enabled F t tR tD3 tD4 t D4 t D4 t tSU HD RSERO RSIG RCHCLK RCHBLK 1 RSYNC 2 RSYNC RSYSCLK SL t tSP SH t t D4 RMSYNC SEE NOTE 3 NOTE 1 RSYNC IS IN THE OUTPUT MODE NOTE...

Page 330: ...DS33R11 Ethernet Mapper with Integrated T1 E1 J1 Transceiver 330 of 344 Figure 13 15 Receive Line Interface Timing t F t R RPOSI RNEGI RDCLKI CL t tCP CH t tSU tHD tDD RPOSO RNEGO RDCLKO LL t tLP LH t...

Page 331: ...ristics Backplane Clock Synthesis VDD 3 3V 5 TA 40 C to 85 C Note 1 Figure 13 16 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Delay RCLKO to BPCLK tD1 10 ns Note Timing parameters in this table are g...

Page 332: ...3 448 ns 20 0 5 tSP TSYSCLK Pulse Width tSP 20 0 5 tSP ns TSYNC or TSSYNC Setup to TCLKT or TSYSCLK Falling tSU 20 ns TSYNC or TSSYNC Pulse Width tPW 50 ns TSERI TSIG TDATA TPOSI TNEGI Setup to TCLKT...

Page 333: ...C TLINK TLCLK TCHBLK tD2 tD2 tD2 t t t t t t HD SU D2 SU HD D1 tHD 2 5 TESO tSU NOTE 1 TSYNC IS IN THE OUTPUT MODE IOCR1 1 1 NOTE 2 TSYNC IS IN THE INPUT MODE IOCR1 1 0 NOTE 3 TSERI IS SAMPLED ON THE...

Page 334: ...SP TSSYNC TCHBLK tD3 tD3 t t tSU HD SU tHD NOTE 1 TSERI IS ONLY SAMPLED ON THE FALLING EDGE OF TSYSCLK WHEN THE TRANSMIT SIDE ELASTIC STORE IS ENABLED NOTE 2 TCHCLK AND TCHBLK ARE SYNCHRONOUS WITH TSY...

Page 335: ...k Period t1 1000 ns JTCLK Clock High Low Time Note 2 t2 t3 50 500 ns JTCLK to JTDI JTMS Setup Time t4 2 ns JTCLK to JTDI JTMS Hold Time t5 2 ns JTCLK to JTDO Delay t6 2 50 ns JTCLK to JTDO HIZ Delay t...

Page 336: ...ee Table 14 1 The DS33R11 contains the following as required by IEEE 1149 1 Standard Test Access Port and Boundary Scan Architecture Test Access Port TAP TAP Controller Instruction Register Bypass Reg...

Page 337: ...ata registers selected by the current instruction If the instruction does not call for a parallel load or the selected register does not allow parallel loads the test register will remain at its curre...

Page 338: ...he serial output The parallel register as well as all test registers remains at their previous states A rising edge on JTCLK with JTMS HIGH will move the controller to the Exit1 IR state A rising edge...

Page 339: ...parallel output and is 3 bits in length When the TAP controller enters the Shift IR state the instruction shift register is connected between JTDI and JTDO While in the Shift IR state a rising edge o...

Page 340: ...on register the following actions occur Once enabled via the Update IR state the parallel outputs of all digital output pins are driven The boundary scan register is connected between JTDI and JTDO Th...

Page 341: ...s the identification register and is used in conjunction with the IDCODE instruction and the Test Logic Reset state of the TAP controller 14 4 1 Boundary Scan Register This register contains both a sh...

Page 342: ...he mandatory X01 pattern Shifting the TDI pin to the TDO pin through the bypass shift register An asynchronous reset occurs while shifting Figure 14 3 JTAG Functional Timing JTCLK JTRST JTMS JTDI JTDO...

Page 343: ...43 of 344 15 PACKAGE INFORMATION The package drawing s in this data sheet may not reflect the most current specifications The package number provided for each package is a link to the latest package o...

Page 344: ...he built in REF_CLKO output clock to drive this input Also removed from the fifth bullet the sentence This output clock can be used as an input to REF_CLK allowing the user to have one less oscillator...

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