DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
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Register Name:
TR.RSCD1
Register Description:
Receive Spare-Code Definition Register 1
Register Address:
BEh
Bit
# 7 6 5 4 3 2 1 0
Name
C7 C6 C5 C4 C3 C2 C1 C0
Default
0 0 0 0 0 0 0 0
Note:
Writing this register resets the detector’s integration period.
Bit 7: Receive Spare-Code Definition Bit 7 (C7).
First bit of the repeating pattern.
Bit 6: Receive Spare-Code Definition Bit 6 (C6).
A don’t care if a 1-bit length is selected.
Bit 5: Receive Spare-Code Definition Bit 5 (C5).
A don’t care if a 1-bit or 2-bit length is selected.
Bit 4: Receive Spare-Code Definition Bit 4 (C4).
A don’t care if a 1-bit to 3-bit length is selected.
Bit 3: Receive Spare-Code Definition Bit 3 (C3).
A don’t care if a 1-bit to 4-bit length is selected.
Bit 2: Receive Spare-Code Definition Bit 2 (C2).
A don’t care if a 1-bit to 5-bit length is selected.
Bit 1: Receive Spare-Code Definition Bit 1 (C1).
A don’t care if a 1-bit to 6-bit length is selected.
Bit 0: Receive Spare-Code Definition Bit 0 (C0).
A don’t care if a 1-bit to 7-bit length is selected.
Register Name:
TR.RSCD2
Register Description:
Receive Spare Code Definition Register 2
Register Address:
BFh
Bit
# 7 6 5 4 3 2 1 0
Name
C7 C6 C5 C4 C3 C2 C1 C0
Default
0 0 0 0 0 0 0 0
Bits 0 – 7: Receive Spare-Code Definition Bits 0–7 (C0–C7).
A don’t care if a 1-bit to 7-bit length is selected.
