DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
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2.5 Additional HDLC Controllers in the Integrated T1/E1/J1 Transceiver
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Two additional independent HDLC controllers
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Fast load and unload features for FIFOs
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SS7 support for FISU transmit and receive
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Independent 128-byte Rx and Tx buffers with interrupt support
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Access FDL, Sa, or single/multiple DS0 channels
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DS0 access includes Nx64 or Nx56
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Compatible with polled or interrupt driven environments
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Bit-oriented code (BOC) support
2.6 Committed Information Rate (CIR) Controller
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CIR Rate controller limits transmission of data from the Ethernet interface to the serial interface
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CIR granularity at 512kbit/s
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CIR averaging for smoothing traffic peaks
2.7 SDRAM
Interface
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Interface for 128Mb, 32-bit-wide SDRAM
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SDRAM Interface speed up to 100MHz
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Auto refresh timing
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Automatic precharge
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Master clock provided to the SDRAM
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No external components required for SDRAM connectivity
2.8 MAC
Interface
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MAC port with standard MII (less TX_ER) or RMII
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10Mbps and 100Mbps Data rates
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Configurable DTE or DCE modes
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Facilitates auto-negotiation by host microprocessor
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Programmable half and full-duplex modes
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Flow control for both half-duplex (back-pressure) and full-duplex (PAUSE) modes
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Programmable Maximum MAC frame size up to 2016 bytes
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Minimum MAC frame size: 64 bytes
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Discards frames greater than programmed maximum MAC frame size and runt, nonoctet bounded, or
bad-FCS frames upon reception
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Configurable for promiscuous broadcast-discard mode.
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Programmable threshold for SDRAM queues to initiate flow control and status indication
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MAC loopback support for transmit data looped to receive data at the MII/RMII interface
