Maverick EP7312, User Manual

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2. EP7312 FUNCTIONAL DESCRIPTION
The EP7312 device is a single-chip embedded controller designed to be used in low-cost and ultra-low-
power applications. Operating at 74 MHz, the EP7312 delivers approximately 66 Dhrystone 2.1 MIPS of
sustained performance (74 MIPS peak). This is approximately the same as a 100 MHz Pentium-based PC.
The EP7312 contains the following functional blocks:
• ARM720T processor which consists of the following functional sub-blocks:
- ARM7TDMI CPU core (which supports the logic for the Thumb instruction set, core debug, enhanced multiplier,
JTAG, and the Embedded ICE) running at a dynamically programmable clock speed of 18 MHz, 36 MHz, 49 MHz, or
74 MHz.
- Memory Management Unit (MMU) compatible with the ARM710 core (providing address translation and a 64-entry
translation lookaside buffer) with added support for Windows CE.
- 8 kbytes of unified instruction and data cache with a four-way set associative cache controller.
- Write buffer
• 48 kbytes (0x9600) of on-chip SRAM that can be shared between the LCD controller and general ap-
plication use.
• Memory interfaces for up to 6 independent 256 Mbyte expansion segments with programming wait
states.
• 27 bits of general purpose I/O - multiplexed to provide additional functionality where necessary.
• Digital Audio Interface (DAI) for connection to CD-quality DACs and CODECs.
• Interrupt controller
• Advanced system state control and power management.
• Two full-duplex 16550A compatible UARTs with 16-byte transmit and receive FIFOs.
• IrDA SIR protocol controller capable of speeds up to 115.2 kbits/s.
• Programmable 1-, 2-, or 4-bit-per-pixel LCD controller with 16-level grayscaler.
• Programmable frame buffer start address, allowing a system to be built using only internal SRAM for
memory.
• On-chip boot ROM programmed with serial load boot sequence.
• Two 16-bit general purpose timer counters.
• A 32-bit Real Time Clock (RTC) and comparator.
• Dedicated LED flasher pin driven from the RTC with programmable duty ratio (multiplexed with a
GPIO pin).
• Two synchronous serial interfaces for Micro-wire or SPI peripherals such as ADCs, one supporting
both the master and slave mode and the other supporting only the master mode.
• Full JTAG boundary scan and Embedded ICE support.
• Two programmable pulse-width modulation interfaces.
• An interface to one or two Cirrus Logic CL-PS6700 PC Card controller devices to support two PC Card
slots.
• Direct SDRAM interface operates at up to 36.864 MHz with 4 internal banks totaling 256 Mbits in
size. The SDRAM interface can be configured for 16-bit or 32-bit wide accesses.
• Oscillator and phase-locked loop (PLL) to generate the core clock speeds of 18.432 MHz,
36.864 MHz, 49.152 MHz, and 73.728 MHz from an external 3.6864 MHz crystal.
• An alternative external clock input at 13 MHz.
• A low-power 32.768 kHz oscillator that generates the RTC.