104
DS508UM1
6.21
State Control Registers
6.21.1
STDBY — Enter the Standby State Location
ADDRESS: 0x8000.0840
A write to this location will put the system into the Standby State by halting the main oscillator. A write
to this location while there is an active interrupt will have no effect.
Notes: 1)
Before entering the Standby State, the LCD Controller should be disabled. The LCD con-
troller should be enabled on exit from the Standby State.
2) If the EP7312 is attempting to get into the Standby State when there is a pending interrupt
request, it will not enter into the low power mode. The instruction will get executed, but
the processor will ignore the command.
6.21.2
HALT — Enter the Idle State Location
ADDRESS: 0x8000.0800
A write to this location will put the system into the Idle State by halting the clock to the processor until
an interrupt is generated. A write to this location while there is an active interrupt will have no effect.
6.22
SS2 Registers
6.22.1
SS2DR — Synchronous Serial Interface 2 Data Register
ADDRESS: 0x8000.1500
This is the 16-bit-wide data register for the full-duplex master / slave SSI2 synchronous serial inter-
face. Writing data to this register will initiate a transfer. Writes need to be word writes and the bottom
16 bits are transferred to the TX FIFO. Reads will be 32 bits as well with the lower 16 bits containing
RX data, and the upper 16-bits should be ignored. Although the interface is byte-oriented, data is writ-
ten in two bytes at a time to allow higher bandwidth transfer. It is up to the software to assemble the
bytes for the data stream in an appropriate manner.
All reads / writes to this register must be word reads / writes.
6.22.2
SS2POP — Synchronous Serial Interface 2 Pop Residual Byte
ADDRESS: 0x8000.16C0
This is a write-only location which will cause the contents of the RX shift register to be popped into
the RX FIFO, thus enabling a residual byte to be read. The data value written to this register is ig-
nored. This location should be used in conjunction with the RESVAL and RESFRM bits in the
SYSFLG2 register.
Summary of Contents for EP7312
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