Maverick EP7312, User Manual

Page: 38 / 122

DS508UM1 39
2.15 Internal UARTs (Two) and SIR Encoder
The EP7312 contains two built-in UARTs that offers similar functionality to National Semiconductor’s
16C550A device. Both UARTs can support bit rates of up to 115.2 kbits/s and include two 16-byte FIFOs:
one for receive and one for transmit.
One of the UARTs (UART1) supports the three modem control input signals CTS, DSR, and DCD. The
additional RI input, and RTS and DTR output modem control lines are not explicitly supported but can be
implemented using GPIO ports in the EP7312. UART2 has only the RX and TX pins.
UART operation and line speeds are controlled by the UBLCR1 (UART bit rate and line control). Three
interrupts can be generated by UART1: RX, TX, and modem status interrupts. Only two can be generated
by UART2: RX and TX. The RX interrupt is asserted when the RX FIFO becomes half full or if the FIFO
is non-empty for longer than three character length times with no more characters being received. The TX
interrupt is asserted if the TX FIFO buffer reaches half empty. The modem status interrupt for UART1 is
generated if any of the modem status bits change state. Framing and parity errors are detected as each byte
is received and pushed onto the RX FIFO. An overrun error generates an RX interrupt immediately. All
error bits can be read from the 11-bit wide data register. The FIFOs can also be programmed to be one byte
depth only (i.e., like a conventional 16450 UART with double buffering).
The EP7312 also contains an IrDA (Infrared Data Association) SIR protocol encoder as a post-processing
stage on the output of UART1. This encoder can be optionally switched into the TX and RX signals of
UART1, so that these can be used to drive an infrared interface directly. If the SIR protocol encoder is en-
abled, the UART TXD1 line is held in the passive state and transitions of the RXD1 line will have no effect.
The IrDA output pin is LEDDRV, and the input from the photodiode is PHDIN. Modem status lines will
cause an interrupt (which can be masked) irrespective of whether the SIR interface is being used.
Both the UARTs operate in a similar manner to the industry standard 16C550A. When CTS is deasserted
on the UART, the UART does not stop shifting the data. It relies on software to take appropriate action in
response to the interrupt generated.
Baud rates supported for both the UARTs are dependent on frequency of operation. When operating from
the internal PLL, the interface supports various baud rates from 115.2 kbits/s downwards. The master clock
frequency is chosen so that most of the required data rates are obtainable exactly. When operating with a
13.0 MHz external clock source, the baud rates generated will have a slight error, which is less than or
equal to 0.75%. The rates (all measured in kbits/s) obtainable from the 13 MHz clock include: 9.6, 19.2,
38, 58, and 115.2. See UBRLCR1-2 UART1-2 Bit Rate and Line Control Registers for full details of the
available bit rates in the 13 MHz mode.