102
DS508UM1
6.19
STFCLR — Clear All “Start Up Reason” Flags Location
ADDRESS: 0x8000.05C0
A write to this location will clear all the “Start Up Reason” flags in the system flags status register SYS-
FLG. The “Start Up Reason” flags should first read to determine the reason why the chip was started
(i.e., a new battery was installed). Any value may be written to this location.
6.20
End Of Interrupt Locations
The “End of Interrupt” locations that follow are written to after the appropriate interrupt has been ser-
viced. The write is performed to clear the interrupt status bit, so that other interrupts can be serviced.
Any value may be written to these locations.
6.20.1
BLEOI Battery Low End of Interrupt
ADDRESS: 0x8000.0600
A write to this location will clear the interrupt generated by a low battery (falling edge of BATOK with
nEXTPWR high).
6.20.2
MCEOI Media Changed End of Interrupt
ADDRESS: 0x8000.0640
A write to this location will clear the interrupt generated by a falling edge of the nMEDCHG input pin.
6.20.3
TEOI Tick End of Interrupt Location
ADDRESS: 0x8000.0680
A write to this location will clear the current pending tick interrupt and tick watch dog interrupt.
Bit
Description
0-7 or 0-6
ADC Configuration Byte: When the ADCCON control bit in the SYSCON3 register = 0, this is
the 8-bit configuration data to be sent to the ADC. When the ADCCON control bit in the
SYSCON3 register = 1, this field determines the length of the ADC configuration data held in the
ADC Configuration Extension field for sending to the ADC.
8-12 or 7-12
Frame length: The Frame Length field is the total number of shift clocks required to complete a
data transfer.
In default mode, MAX148/9 (and for many ADCs), this is 25 = (8 for configuration byte + 1 null bit
+ 16 bits result).
In extended mode, AD7811/12, this is 23 = (10 for configuration byte + 3 null + 10 bits result).
13
SMCKEN: Setting this bit will enable a free running sample clock at twice the programmed ADC
clock frequency to be output on the SMPLCK pin.
14
TXFRMEN: Setting this bit will cause an ADC data transfer to be initiated. The value in the ADC
configuration field will be shifted out to the ADC and depending on the frame length programmed,
a number of bits will be captured from the ADC. If the SYNCIO register is written to with the
TXFRMEN bit low, no ADC transfer will take place, but the Frame length and SMCKEN bits will
be affected.
16-31
ADC Configuration Extension: When the ADCCON control bit in the SYSCON3 register = 0.
When the ADCCON control bit in the SYSCON3 register = 1, this field is the configuration data to
be sent to the ADC. The ADC Configuration Extension field length is determined by the value
held in the ADC Configuration Length field (SYNCIO[0-6]).
Table 55. SYNCIO
Summary of Contents for EP7312
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