4/29/2020
Godson 3A2000 / 3B2000 Processor User Manual
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'0' – no errors
6
TE
1
R
Transmission is empty
'1' – Both the transmission FIFO and the transmission shift register are empty. give
Clear when the transmit FIFO writes data
'0' – with data
5
TFE
1
R
Transmit FIFO bit empty representation bit
'1' – The current transmit FIFO is empty, write data to the transmit FIFO
Time zero
'0' – with data
4
BI
1
R
Interrupt interruption bit
'1'-Start bit + data + parity bit + stop bit received
Is 0, that is interrupted
'0'-no interruption
3
FE
1
R
Frame error indication bit
'1' – received data has no stop bit
'0' – no errors
2
PE
1
R
Parity bit error indicates bit
'1'-The current received data has a parity error
'0' – no parity error
1
OE
1
R
Data overflow indication bit
'1'-There is data overflow
'0' – no overflow
0
DR
1
R
Receive data valid representation bit
'0' – No data in FIFO
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Godson 3A2000 / 3B2000 Processor User Manual Part 1
'1' – There is data in the FIFO
When reading this register, LSR [4: 1] and LSR [7] are cleared, and LSR [6: 5] is writing data to the transmit FIFO
Cleared according to the time, LSR [0] judges the receive FIFO.
11.3.8
MODEM status register ( MSR )
Chinese name: Modem Status Register
Register bit width: [7: 0]
Offset: 0x06
Reset value: 0x00
Bit field
Bit field name
Bit width access
description
7
CDCD
1
R
Inverse of DCD input value, or connect to Out2 in loopback mode
6
CRI
1
R
Inverse of RI input value, or connect to OUT1 in loopback mode