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Godson 3A2000 / 3B2000 Processor User Manual
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10.5.17
Send buffer debug register
Send buffer debugging register is used to manually set the number of buffers at the sending end of the HT controller.
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Godson 3A2000 / 3B2000 Processor User Manual Part 1
Adjust the number of different send buffers.
Offset: 0x108
Reset value: 0x00000000
Name: Send cache debug register
Table 10-68 Send Buffer Debug Register
Bit field
Bit field name
Bit width reset value Visit description
31:30 Reserved
2
0x0
R
Keep
29
Tx_neg
1
0x0
R / W
Debugging symbols are cached on the sending end
0: increase the corresponding number
1: Reduce (number of corresponding reg 1)
28
Tx_buff_adj_en
1
0x0
R / W
Buffer debugging enable register on the sending end
0-> 1: make the value of this register increase and decrease
27:24 R_DATA_txadj
4
0x0
R / W
Increase and decrease the number of R channel data buffers at the sending end
When tx_neg is 0, increase R_DATA_txadj;
When tx_neg is 1, reduce R_DATA 1
23:20 NPC_DATA_txadj 4
0x0
R / W
Number of data buffers at the sender's NPC channel
When tx_neg is 0, increase NPC_DATA_txadj;
When tx_neg is 1, reduce NPC_DATA 1
19:16 PC_DATA_txadj
4
0x0
R / W
Increase or decrease the number of PC channel data buffers at the sending end
When tx_neg is 0, add PC_DATA_txadj;
When tx_neg is 1, reduce PC_DATA 1
15:12 B_CMD_txadj
4
0x0
R / W
Number of increase and decrease of the command buffer of the B channel of the sending end
When tx_neg is 0, increase B_CMD_txadj;
When tx_neg is 1, reduce B_CMD 1
11: 8
R_CMD_txadj
4
0x0
R / W
Increase and decrease the number of R channel command buffers at the sending end
When tx_neg is 0, increase R_CMD_txadj;
When tx_neg is 1, reduce R_CMD 1
7: 4
NPC_CMD_txadj
4
0x0
R / W
Number of increase / decrease of NPC channel command / data buffer at the sending end
When tx_neg is 0, increase NPC_CMD_txadj;
When tx_neg is 1, reduce NPC_CMD 1
3: 0
PC_CMD_txadj
4
0x0
R / W
Increase or decrease the number of PC channel command buffers at the sending end
When tx_neg is 0, increase PC_CMD_txadj;
When tx_neg is 1, reduce PC_CMD 1
10.5.18
PHY impedance matching control register
Used to control the impedance matching enable of the PHY, and set the impedance matching parameters at the transmitter and receiver
Offset: 0x10C
Reset value: 0x00000000
Name: PHY impedance matching control register
Table 10-69 Impedance Matching Control Register
Bit field
Bit field name
Bit width reset value Visit description
31
Tx_scanin_en
1
0x0
R / W TX impedance matching enable
30
Rx_scanin_en
1
0x0
R / W RX impedance matching enable
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