Loongson 3A2000, User Manual, Page: 17 / 126

4/29/2020 Godson 3A2000 / 3B2000 Processor User Manual
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CLKSEL [15: 0] CLKSEL [14]
1'b0 means HT PLL uses differential clock input
CLKSEL [13:12]
2'b00 means the PHY clock is 1.6GHZ
2'b01 indicates that the PHY clock is 3.2GHZ
2'b10 means the PHY clock is 1.2GHz
2'b11 means the PHY clock is 2.4GHz
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Godson 3A2000 / 3B2000 Processor User Manual Part 1
CLKSEL [11:10]
2'b00 indicates that the HT controller clock is divided by 8 of the PHY clock
2'b01 indicates that the HT controller clock is divided by 4 of the PHY clock
2'b10 means the HT controller clock is divided by 2 of the PHY clock
2'b11 indicates that the HT controller clock is SYSCLOCK
Note: When CLKSEL [13:10] == 4'b1111, the HT controller clock is in bypass mode and used directly
External input 100MHz reference clock
MEM clock control
signal effect
CLKSEL [9: 5]
5'b11111 means MEM clock directly uses memclk
5'b01111 indicates that the MEM clock is set by software. For the setting method, see
2.6 Description
In other cases, the MEM clock is
memclk * (clksel [8: 5] +30) / (clksel [9] +3)
Note:
memclk * (clksel [8: 5] +30) must be 1.2GHz ~ 3.2GHz
memclk is the input reference clock, which must be 20 ~ 40MHz
CORE clock control
signal effect
CLKSEL [4: 0]
5'b11111 indicates that the CORE clock directly uses sysclk
5'b011xx indicates that the CORE clock is set by software. For the setting method, see
Instructions in Section 2.6 .
5'b01111 is normal working mode, otherwise it is debugging mode
5'b0110x means FIFO depth is set to 2
5'b011x0 means DCDL control mode
In other cases, the CORE clock is
sysclk * (clksel [3: 0] +30) / (clksel [4] +1)
Note:
sysclk * (clksel [3: 0] +30) must be 1.2GHz ~ 3.2GHz
sysclk is the input reference clock, which must be 20 ~ 40MHz
PCI_CONFIG [7: 0]
IO configuration control
7 HT bus cold start is forced to 1.0 mode
6: 4 needs to be set to 000
3 PCI master mode
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