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Godson 3A2000 / 3B2000 Processor User Manual
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● Memory commands are combined and sorted to improve overall bandwidth
● Configure register read and write ports, you can modify the basic parameters of the memory device
● Built-in dynamic delay compensation circuit (DCC) for reliable transmission and reception of data
● The ECC function can detect 1-bit and 2-bit errors on the data path, and can automatically detect 1-bit errors.
Error correction
● Support 133-667MHZ working frequency
9.2 DDR2 / 3 SDRAM read operation protocol
The protocol of DDR2 / 3 SDRAM read operation is shown in Figure 11-2. In the figure, the command (Command, CMD for short) consists of
RAS_n, CAS_n and WE_n are composed of three signals. For read operations, RAS_n = 1, CAS_n = 0, and WE_n = 1.
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Godson 3A2000 / 3B2000 Processor User Manual Part 1
Figure 9-1 DDR2 SDRAM read operation protocol
In the figure above, Cas Latency (CL) = 3, Read Latency (RL) = 3, and Burst Length = 8.
9.3 DDR2 / 3 SDRAM write operation protocol
The protocol of DDR2 / 3 SDRAM write operation is shown in Figure 11-3. The command CMD in the figure is composed of RAS_n, CAS_n and
WE_n is composed of three signals. For write operations, RAS_n = 1, CAS_n = 0, and WE_n = 0. In addition, with the read operation
Differently, write operations require DQM to identify the mask of the write operation, that is, the number of bytes to be written. DQM is the same as the DQs signal in the figure
step.
Figure 9-2 DDR2 SDRAM write operation protocol
In the above picture, Cas Latency (CL) = 3, Write Latency (WL) = Read Latency (RL) – 1 = 2,
Burst Length = 4.