
4/29/2020
Godson 3A2000 / 3B2000 Processor User Manual
89
REG0 [15: 0]
LPC_SYNC_TIMEOUT
Read-write 0
LPC access timeout counter
REG1
REG1 [31:31]
LPC_MEM_IS_FWH
Read-write 0
LPC Memory Space Firmware
Memory access type settings
REG1 [17: 0]
LPC_INT_EN
Read-write 0
LPC SIRQ interrupt enable
REG2
REG2 [17: 0]
LPC_INT_SRC
Read-write 0
LPC SIRQ interrupt source indication
REG3
REG3 [17: 0]
LPC_INT_CLEAR
write
0
LPC SIRQ interrupt clear
11.3 UART controller
The UART controller has the following features
● Full duplex asynchronous data receiving / sending
● Programmable data format
● 16-bit programmable clock counter
● Support receiving timeout detection
● Multi-interrupt system with arbitration
● Only work in FIFO mode
● Compatible with NS16550A in register and function
The chip integrates two UART interfaces, the function registers are exactly the same, but the access base address is different.
The base address of the physical address of the UART0 register is 0x1FE001E0.
The base address of the physical address of the UART1 register is 0x1FE001E8.
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Godson 3A2000 / 3B2000 Processor User Manual Part 1
11.3.1
Data Register ( DAT )
Chinese name: Data Transfer Register
Register bit width: [7: 0]
Offset: 0x00
Reset value: 0x00
Bit field
Bit field name
Bit width access
description
7: 0
Tx FIFO
8
W
Data transfer register
11.3.2
Interrupt enable register ( IER )
Chinese name: Interrupt enable register
Register bit width: [7: 0]
Offset: 0x01
Reset value: 0x00
Bit field
Bit field name
Bit width access
description