4/29/2020
Godson 3A2000 / 3B2000 Processor User Manual
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Table 10-64 HT bus P2P address window 1 enable (external access) register definition
Bit field
Bit field name
Bit width reset value Visit description
31
ht_p2p_image1_en 1
0x0
R / W HT bus P2P address window 1, enable signal
30
ht_p2p_image1_
trans_en
1
0x0
R / W HT bus P2P address window 1, mapping enable signal
29: 0
ht_p2p_image1_
trans [53:24]
16
0x0
R / W HT bus P2P address window 1, the translated address [53:24]
Offset: 0x164
Reset value: 0x00000000
Name: HT bus P2P address window 1 base address (external access)
Table 10-65 HT bus P2P address window 1 base address (external access) register definition
Bit field
Bit field name
Bit width reset value Visit description
87
Page 92
Godson 3A2000 / 3B2000 Processor User Manual Part 1
Bit field
Bit field name
Bit width reset value Visit description
31:16 ht_p2p_image1_
base [39:24]
16
0x0
R / W HT bus P2P address window 1, address base address [39:24]
15: 0
ht_p2p_image1_
mask [39:24]
16
0x0
R / W HT bus P2P address window 1, address masked [39:24]
10.5.15
Command send buffer size register
The command sending buffer size register is used to observe the number of buffers available for each command channel at the sending end.
Offset: 0x100
Reset value: 0x00000000
Name: Command send buffer size register
Table 10-66 Command Send Buffer Size Register
Bit field
Bit field name
Bit width reset value Visit description
31:24 B_CMD_txbuffer
8
0x0
R
Number of B channel command buffers at the sending end
2316 R_CMD_txbuffer
8
0x0
R
Number of R channel command buffers at the sending end
15: 8
NPC_CMD_txbuffer 8
0x0
R
Number of NPC channel command buffers at the sending end
7: 0
PC_CMD_txbuffer 8
0x0
R
Number of PC channel command buffers at the sending end
10.5.16
Data transmission buffer size register
The data transmission buffer size register is used to observe the number of buffers available for each data channel at the sending end.
Offset: 0x104
Reset value: 0x00000000
Name: Data transmission buffer size register
Table 10-67 Data transmission buffer size register
Bit field
Bit field name
Bit width reset value access description
31:24 Reserved
8
0x0
R
Keep
2316 R_DATA_txbuffer
8
0x0
R
Number of R channel data buffers at the sending end
15: 8
NPC_DATA_txbuffer 8
0x0
R
Number of NPC channel data buffers at the sending end
7: 0
PC_DATA_txbuffer 8
0x0
R
Number of PC channel data buffers at the sending end