TME-104-CLR-86DX-R0V2.doc
Rev. 0.2
37(
44
)
Watchdog
There are 3 Watchdogs available. WDT0 and WDT1 are provided by the Vortex86DX. Additionally the SMC
contains a third Watchdog.
WDT0 example:
#include
<
sys
/
io
.
h
>
#include
<
stdio
.
h
>
#define
WDT0_INDEX 0x22
#define
WDT0_DATA 0x23
int
main
()
{
unsigned int
wdog_time
= (
0x20L
*
0x500L
);
unsigned char
trig
=
0
,
wdog_en
=
0
,
reset_cntr
=
0
;
if
(
iopl
(
3
) !=
0
)
{
printf
(
"IOPL error
\
n"
);
return
1
;
}
//Unlock sequence
outb
(
0x13
,
WDT0_INDEX
);
outb
(
0xC5
,
WDT0_DATA
);
//set time counter register: 0x3b, 0x3a, 0x39
outb
(
0x3b
,
WDT0_INDEX
);
//D23...D16
outb
((
wdog_time
>>
16
) &
0xFF
,
WDT0_DATA
);
outb
(
0x3a
,
WDT0_INDEX
);
//D15...D8
outb
((
wdog_time
>>
8
) &
0xFF
,
WDT0_DATA
);
outb
(
0x39
,
WDT0_INDEX
);
//D7...D0
outb
(
wdog_time
&
0xFF
,
WDT0_DATA
);
//set trigger: 0x38
outb
(
0x38
,
WDT0_INDEX
);
trig
=
inb
(
WDT0_DATA
);
trig
&=
0x0F
;
trig
|=
0xD0
;
//0xD0 = system reset
outb
(
0x38
,
WDT0_INDEX
);
outb
(
trig
,
WDT0_DATA
);
//enable wdog: 0x37
outb
(
0x37
,
WDT0_INDEX
);
wdog_en
=
inb
(
WDT0_DATA
);
wdog_en
|=
0x40
;
//bit6 = 1 --> enable WDT0
outb
(
0x37
,
WDT0_INDEX
);
outb
(
wdog_en
,
WDT0_DATA
);
printf
(
"Watchdog active
,
resetting counter
,
Press CLRT
+
C to stop resetting
\
n"
);
//reset counter: 0x3C
while
(
1
)
{
outb
(
0x3C
,
WDT0_INDEX
);
reset_cntr
=
inb
(
WDT0_DATA
);
reset_cntr
|=
0x40
;
//bit6 = 1 --> reset timer counter
outb
(
0x3C
,
WDT0_INDEX
);
outb
(
reset_cntr
,
WDT0_DATA
);
}
//Lock sequence
outb
(
0x13
,
WDT0_INDEX
);
outb
(
0x00
,
WDT0_DATA
);
return
0
;
}