Lippert Components Cool LiteRunner-86DX, Technical Manual, Page: 32 / 53

TME-104-CLR-86DX-R0V2.doc Rev. 0.2
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3.16 JTAG-CPU (BIOS recovery)
The BIOS flash is integrated in the Vortex86DX.
The BIOS can be updated with an update tool via the internal SPI bus.
Full BIOS recovery can be done via JTAG. The JTAG port of the Vortex86DX can be found next to the RS485
termination connector.
Needed for full BIOS Recovery: LPT-to-JTAG cable, BIOS file and JFlash
Connector type IDC12 pin header 2.54 mm
Matching connector IDC12 pin female connector 2.54 mm
Pin Signal Signal
1 +5 Volt +3.3 Volt
2 GND GND
3 V86DX _TCK FPGA _TCK
4 V86DX _TDO FPGA _TDO
5 V86DX_TDI FPGA _TDI
6 V86DX _TMS FPGA _TMS
3.17 FPGA (Field Programmable Gate Array)
For the first time a LiPPERT board has a FPGA freely useable for I/O extension by the customer. It is a Xilinx
Spartan-3A FPGA with 200K Gates. The programming software (“ISE WebPack”) is freeware and can be
downloaded from the Xilinx home page.
On hardware side the FPGA is physically connected to the LPC bus and the COM4 of the Vortex86DX. By
implementing a LPC- or UART- slave device into the FPGA a data exchange can take place between FPGA and
Vortex86DX.
The FPGA can boot from JTAG or SPI-Flash. The boot mode is SMC controlled and can be changed with the
LEMT tool.
For using JTAG, a Xilinx Platform-Cable (USB or LPT) is needed.
The SPI-Flash can be programmed externally over the GP-SPI pins on the Supervisory (e.g. with the Xilinx
Platform-Cable) or internally from Vortex86DX over GP-SPI (uses GPIO00 ... 04) with the special flash tool
V86DX_GPSPI (downloadable on the LiPPERT homepage).
Note: For further information see CLR86DX-FPGA-Manual
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