Lippert Components Cool LiteRunner-86DX, Technical Manual, Page: 33 / 53

TME-104-CLR-86DX-R0V2.doc Rev. 0.2
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3.18 JTAG-FPGA
The JTAG port of the FPGA can be found between JTAG-CPU port and COM1. The JTAG port can be used to
program the FPGA. Therefore the FPGA boot mode has to be switched to JTAG in the LEMT tool
Connector type IDC12 pin header 2.54 mm
Matching connector IDC12 pin female connector 2.54 mm
Pin Signal Signal
1 +5 Volt +3.3 Volt
2 GND GND
3 V86DX _TCK FPGA _TCK
4 V86DX _TDO FPGA _TDO
5 V86DX_TDI FPGA _TDI
6 V86DX _TMS FPGA _TMS
3.19 FPGA-I/O Connectors
The I/Os are routed directly to four IDC30 (2mm) connectors. That offers the possibility of a flexible and low-cost
Board-to-board or board-to-wire connection. Two connectors are organized as differential pairs and “Global
Clock” usage pins. The other two are single ended organized.
Differential signal and “Global Clock” connector 1 (X13)
Connector type IDC30 pin header 2.0 mm
Matching connector
Pin
IDC30 pin female connector 2.0 mm
Signal Pin Signal
1
3.3 V
7
2 3.3 V
3 FPGA_IO_DIFF0_P 4 FPGA_IO_DIFF0_N
5 FPGA_IO_DIFF1_P 6 FPGA_IO_DIFF1_N
7 FPGA_IO_DIFF2_P 8 FPGA_IO_DIFF2_N
9 FPGA_IO_DIFF3_P 10 FPGA_IO_DIFF3_N
11 FPGA_IO_DIFF4_P 12 FPGA_IO_DIFF4_N
13 FPGA_IO_DIFF5_P 14 FPGA_IO_DIFF5_N
15 FPGA_IO_GCLK_DIFF6_P 16 FPGA_IO_GCLK_DIFF6_N
17 FPGA_IO_GCLK_DIFF7_P 18 FPGA_IO_GCLK_DIFF7_N
19 FPGA_IO_DIFF8_P 20 FPGA_IO_DIFF8_N
21 FPGA_IO_DIFF9_P 22 FPGA_IO_DIFF9_N
23 FPGA_IO_DIFF10_P 24 FPGA_IO_DIFF10_N
25 FPGA_IO_DIFF11_P 26 FPGA_IO_DIFF11_N
27 FPGA_IO_DIFF12_P 28 FPGA_IO_DIFF12_N
29 GND 30 GND
7
0.5 A is the maximum current for that pin
X13
X19