LTC4110
24
4110fb
The micropower shutdown state will be maintained if the
DCIN supply is removed and suffi cient battery voltage is
present (V
BAT
≥ 2.7V). When DCIN is reapplied as detected
by the UVLO (see V
UVI
), regardless of the level of the
SHDN pin, the shutdown state is automatically cancelled.
Register reset state is cancelled until DCIN is reapplied as
determined by the DCDIV pin.
The voltage across the external current programming
resistor R
SNS(BAT)
is averaged by the RC network con-
nected to the CSP and CSN pins and then amplifi ed by a
ratio of R
ICHG
/(R
CSP1
+ R
CSP2
). This amplifi ed voltage is
compared with the bandgap reference through the cur-
rent loop error amplifi er to adjust the I
TH
pin which sets
the current comparator threshold to maintain a constant
charging current. Once the battery voltage rises to close
to the programmed fl oat voltage, the voltage loop error
amplifi er gradually pulls the I
TH
pin low, reduces the charg-
ing current and maintain a constant voltage charging.
C/x CHARGE TERMINATION
LTC4110 monitors the charging current through the volt-
age on the I
CHG
pin, once the current drops below 20% of
the bulk charging current, an internal C/x comparator is
tripped, and the LTC4110 will enter top-off charge stage
if standard Li-Ion battery mode is selected or release the
GPI01 pin if no-host SLA battery mode is selected. The
actual x value depends on the programmed charging cur-
rent and the C rate of the battery.
x
C
I
CHG
=
• 5
OPERATION
Figure 9. LTC4110 PWM Engine
In shutdown; charge, calibration and backup modes are
inhibited, all registers are set to their default states (with
exception of the backup fault bit register), the internal
timer is reset and oscillator disabled, the status pins;
ACPb, GPIO1, GPIO2 and GPIO3 are a high impedance
and the LTC4110 is put into a micropower state. While
in shutdown the SMBus is disabled and the SDA and
SCL pins are high impedance. In addition, the shutdown
state will disconnect loads from the battery to prevent its
discharge as follows:
• The BATID pin is forced to the battery voltage to turn
off the battery P-MOSFETs for isolation of the load from
the battery
• The CHGFET and DCHFET pins are forced to GND to
turn off the fl yback switcher N-MOSFETs
• Current into the BAT pin is minimized. Also the V
DD
and
V
REF
pin voltages will fall to zero.
While in shutdown, the LTC4110 will draw a small current
from battery (I
BSD
) if the DCIN supply is absent. If the SHDN
pin is open an internal weak pull-up current (I
ISD
) pulls the
pin voltage up thereby entering the shutdown state.
PWM OPERATION
A conceptual diagram of the LTC4110 PWM engine is
shown in Figure 9.
Figure 8. Shutdown Control Input
SHDN
LTC4110
SHUTDOWN
4110 F08
5V
I
ISD
V
FB
4110 F09
BAT
R
CSP2
CSP
R
CSP1
R
SNS(BAT)
V
SNS
+
–
–
+
+
+
–
R
CSN2
CSN
INPUT
CURRENT
AMPLIFIER
V
ICHG
=
R
ICHG
/(R
CSP1
+ R
CSP2
)*V
SNS
VOLTAGE
LOOP EA
REFERENCE
VOLTAGE
ADJUSTED BY
V
CHG
PIN
+
–
CURRENT
LOOP EA
BANDGAP
R
CSN1
+
+
I
TH
R
ICHG
I
CHG
+
–
+
–
+
–
