LTC4110
6
4110fb
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime. Specifi c functionality or parametric performance
of the device beyond the limits expressly given in the Electrical
Characteristics table is not implied by these maximum ratings.
Note 2:
The LTC4110E is guaranteed to meet performance specifi cations
from 0°C to 85°C. Specifi cations over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
Note 3:
This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions.
Overtemperature protection will become active at a junction temperature
greater than the maximum operating junction temperature. Continuous
operation above the specifi ed maximum operation temperature may result
in device degradation or failure. Operating junction temperature T
J
(in
°C) is calculated from the ambient temperature T
A
and the average power
dissipation P
D
(in watts) by the formula T
J
= T
A
+
θ
JA
• P
D
.
ELECTRICAL CHARACTERISTICS
The
l
denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at T
A
= 25°C. Unless otherwise specifi ed, V
DCIN
= V
DCOUT
= V
DCDIV
= 12V, V
BAT
= 8.4V,
GND = SGND = CLP = CLN = SHDN = 0V and R
VREF
= 49.9k. All currents into device pins are positive and all currents out of device pins
are negative. All voltages are referenced to GND, unless otherwise specifi ed.
Note 4:
The LTC4110 is idle with no application load. It is not charging
or calibrating the battery and is not in backup or shutdown mode. The
internal clock is running and the SMBus is functional.
Note 5:
Combined current of CSP, CSN and BAT pins set to V
BAT
with no
application load.
Note 6:
C
TH
is defi ned as the sum of capacitance on THA, THB
SafetySignal.
Note 7:
Does not include tolerance of current sense or current
programming resistors.
Note 8:
Given as a per cell voltage referred to the BAT pin (V
BAT
/number of
series cells).
Note 9:
Refer to System Management Bus Specifi cation, Revision 1.1,
section 2.1 for Timing Diagrams and section 8.1, for t
LOW
and t
TIMEOUT
requirements.
Note 10:
Specifi cations over the –5°C to 85°C operating ambient
temperature range are assured by design, characterization and correlation
with statistical process controls.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
REMH
THB Pin Battery Removal Threshold
Hysteresis Voltage
V
THB
Decreasing; Lead Acid Only
25
mV
Logic and Status Output Levels
V
ILS
SCL/SDA Input Pins Low Voltage
l
0.8
V
V
IHS
SCL/SDA Input Pins High Voltage
l
2.1
V
V
OLS
SDA Output Pin Low Voltage
I
PULL-UP
= 350μA
l
0.4
V
V
OLG
ACPb, GPIO1,2,3 Output Pins Low Voltage
I
ACPb
, I
GPIO1
, I
GPIO2
, I
GPIO3
= 10mA
1
V
I
OHG
ACPb, GPIO1,2,3 Output Pins Open
Leakage Current
Outputs Open, V
ACPb
, V
GPIO1,2,3
= 5V
–2
2
μA
V
ILG
GPIO Input Low Voltage
l
1
V
V
IHG
GPIO Input High Voltage
l
1.5
V
V
ILSD
SHDN Input Pin Low Voltage
0.5
V
V
IHSD
SHDN Input Pin High Voltage
2.4
V
I
ISD
SHDN Input Pin Pull-Up Current
V
SHDN
= 2.4V
–3.5
–2
–1
μA
T
LR
Logic Reset Duration After Power-Up
From Zero
V
DCIN
Transition From 0V to 5V in <1ms;
V
BAT
= 0
1
s
SMBus Timing (Note 9)
t
HIGH
SCL Serial Clock High Period
I
PULL-UP
= 350μA, C
LOAD
= 250pF,
R
PU
= 9.31k
l
4
μs
t
LOW
SCL Serial Clock Low Period
I
PULL-UP
= 350μA, C
LOAD
= 250pF,
R
PU
= 9.31k
l
4.7
μs
t
TO
Timeout Period
l
25
ms
t
F
SDA/SCL Fall Time
C
LOAD
= 250pF, R
PU
= 9.31k
l
300
ns
t
SU-STA
Start Condition Set-Up Time
l
4.7
μs
t
HD-STA
Start Condition Hold Time
l
4
μs
t
HD-DAT
SDA to SCL Falling-Edge Hold Time,
Slave Clocking in Data
l
300
ns