LTC4110
46
4110fb
APPLICATIONS INFORMATION
OPERATION WITH DUAL BACKUP SYSTEMS
If a dual backup system consisting of two LTC4110s
each with its own backup battery is needed and a SMBus
is used, each LTC4110 should be programmed by the
SELA pin to have different addresses. If smart batteries
with SMBus are used, a SMBus mux may be required to
selectively address each battery. This mux may also be
used to address the LTC4110. See SMBus Interface section
for more information.
BACKUP OPERATION WITH EXTERNAL BACKUP
SUPPLY REGULATOR
If a dedicated DC regulator with enable inputs is used in
place of an actual battery to supply backup power, the
PowerPath MOSFETs connected to the BATID pin may not
be required. It depends on the regulator’s ability to accept
being back driven by a voltage on the DCOUT pin coming
from some other power source such as DCIN. The ACPb
pin can control the regulator such that it is turned on when
DCIN goes away. However for fastest transient response,
keeping the regulator on may prove to work better. The
output voltage of the regulator should be less than DCOUT
under normal operating conditions so that DCIN is pro-
viding the power to the load. The voltage provided by the
regulator must not be allowed to go below the lower limit
of the DCOUT pin or erratic operation may result.
BACKUP OPERATION WITH A DOWNSTREAM
REGULATOR
Since the backup voltage supplied to the load is not regu-
lated, often some form of a regulator is needed between
the LTC4110 and the actual load. The characteristics of
this regulator should offer high effi ciency when running
from the battery in backup mode to maximize backup
time. Some regulators may need advance warning when
to enter into this mode, which can be accomplished by
using the LTC4110’s ACPb pin.
DCIN TO BATTERY TRANSITION CHATTER REMOVAL
The LTC4110 is designed to automatically switch the bat-
tery to the output load when DCIN is lost. Under certain
conditions, a rapid loss of DCIN can cause the input and
battery ideal diode circuits to chatter. The result is the
transition time between the DCIN FET turning fully off
and the battery FET turning fully on can last in excess
of 200ms with each switching on and off multiple times.
This problem is likely to occur under the following
conditions:
1. Large system load causing the INID pin to be more
than 3V below DCIN.
2. The DCIN and battery voltages are approximately the
same.
3. The DCIN pin goes high impedance very rapidly (less
than 10μs)
Q1 and R1 shown in Figure 20 increase the effective hys-
teresis of the DCDIV pin by using the ACPb pin to drive
Q1. The threshold of Q1 must be less than the V
SUPPLY
to assure the drain of Q1 pulls down to ground when
ACPb is high. R1 sets the amount of increase in negative
hysteresis you need relative to the values chosen for the
DCDIV resistor divider. A 100k is suggested as a starting
point. You will also need to place a capacitor C
ACPDLY
on
the ACPDLY pin. This capacitor in conjunction with resistor
R
VREF
should be set for a delay of 10ms, which is more
than suffi cient to eliminate all the chatter.
Figure 20.
Q1
2N7002
R1
100k
DCDIV
ACPb
4110 F20
