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LTC4110

30

4110fb

OPERATION

LABEL

DESCRIPTION

OVER_TEMP_ALARM

Set to one indicates battery is temperature is out of range. Setting this bit will stop both a calibration process and a
charging process (default = zero).

TERMINATE_DISCHARGE_ALARM Set to one indicates battery requesting discharge termination. Smart battery only. Setting this bit will only stop a

calibration process (default = zero).

BBuStatus() – Read Only. The SMBus host uses this command to read the LTC4110’s status bits.

CAL_ON

Set to one indicates calibration in progress to discharge the battery.

CAL_COMPLETE

Set to one indicates calibration process is complete. Can be used as a battery capacity indicator. Bit is cleared by
CAL_RESET. This bit is available as a status signal output on the GPIO3 pin.

BKUP_ON

Set to one veriﬁ es backup mode is active

GPIO_1_IN

Shows logic state of general purpose I/O Pin #1. This is always enabled.

GPIO_2_IN

Shows logic state of general purpose I/O Pin #2. This is always enabled.

GPIO_3_IN

Shows logic state of general purpose I/O Pin #3. This is always enabled.

CHG_FLT

Set to one indicates battery charge fault.

BKUP_FLT

Set to one indicates battery cell voltage < V

DIS

. This bit state is retained as long as sufﬁ cient V

BAT

is applied. This

bit is available as a status signal output on the GPIO2 port. This bit remains until either the SHDN pin is cycled or
register bits POR_RESET or BUFLT_RST are set when DCOUT returns.

CAL_FLT

Set to one indicates a calibration fault. Calibration terminated early.

CHG_STATE_0

Combined with CHG_STATE_1 indicates phase of charging. 00 = Off, 01 = precharge, 10 = bulk charge, 11 = top off
charge

CHG_STATE_1

See CHG_STATE_0

CHARGE_INHIBITED

Indicates charge inhibited is enabled when set to a one. This as a duplicate of CHARGE_INHIBIT bit in the
ChargerStatus() register.

BBuControl() – Write Only. The SMBus host uses this command to control the LTC4110.

CAL_START

Set to one starts a discharge based calibration of battery (default = self cleared to zero-off)

CAL_RESET

Set to one clears the CAL_FLT as well as the CAL COMPLETE and CAL_ON status bits. If calibration is in progress, it
will also stop the calibration process (default = self cleared to zero-off)

GPIO_1_EN

Set to one enables GPIO1 pin as an output (default = set to one if programming SMBus not used by connecting SELA
pin to 0.5V

REF

, otherwise default = set to zero/GPIO1 high-Z )

GPIO_2_EN

Set to one enables GPIO2 pin as an output (default = set to one if programming SMBus not used by connecting SELA
pin to 0.5V

REF

, otherwise default = set to zero/ GPIO2 high-Z)

GPIO_3_EN

Set to one enables GPIO3 pin as an output (default = set to one if programming SMBus not used by connecting SELA
pin to 0.5V

REF

, otherwise default = set to zero/ GPIO3 high-Z)

GPIO_1_OUT

Programmable logic bit whose state will be reﬂ ected on the GPIO1 pin if the GPIO_1_CHG bit is cleared (default = set
to zero/GPIO1 pulled low)

GPIO_2_OUT

Programmable logic bit whose state will be reﬂ ected on the GPIO2 pin if the GPIO_2_BUFLT bit is cleared (default =
set to zero/GPIO2 pulled low).

GPIO_3_OUT

Programmable logic bit whose state will be reﬂ ected on the GPIO3 pin if the GPIO_3_CALCOM bit is cleared (default
= set to zero/GPIO3 pulled low)

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Summary of Contents for LTC4110

Page 1: ...ttery Manager for Li Ion Polymer Lead Acid NiMH NiCd Batteries and Super Capacitors n Charge and Discharge Battery with Voltages Above and Below the Input Supply Voltage n No Heat Battery Calibration Discharge Using System Load n Automatic Battery Backup with Input Supply Removal Using PowerPath Control n Standalone for Li Ion Polymer SLA and Supercaps n Optional SMBus I2C Support Allows Battery C...

Page 2: ...LP ACPDLY DCDIV SHDN SDA SCL GPI01 GPI02 GPI03 SELA BAT SELC ISENSE SGND CSN CSP ITH ICHG ICAL IPCC THB THA INID DCOUT NC BATID V DD CHGFET DCHFET ACPb V DIS V CAL V CHG V REF TIMER TYPE 23 22 21 20 9 10 11 12 TJMAX 100 C θJA 34 C W EXPOSED PAD PIN 39 IS GND MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE LTC4110EUHF PBF L...

Page 3: ...l 4 5 4 75 5 V VDD MIN Output Voltage IDD 10mA l 4 25 V Charging Performance VFTOL Charge Float Voltage Accuracy 4 20V for Li Ion 2 35V for Lead Acid Note 8 VCHG GND 5 C TA 85 C Note10 40 C TA 85 C l 0 5 0 8 1 0 5 0 8 1 VFATOL Charge Float Voltage Adjust Accuracy 0 3V and 0 3V for Li Ion Batteries 0 15V and 0 15V for Lead Acid Batteries Note 8 l 2 2 IBTOL Bulk Charge Current Accuracy Note 7 VCSP V...

Page 4: ...cid NiMH NiCd 85 50 40 mV mV mV VCATOL Calibration Cut Off Voltage Adjust Accuracy 400mV for Li Ion 300mV for Lead Acid 200mV for NiMH NiCd Note 8 l 1 5 1 5 IFTOL Calibration Current Accuracy Note 7 VCSP VCSN 100mV l 5 5 IVCAL VCAL Pin Leakage Current VCAL 1 25V 100 100 nA IBDT Back Drive Current Limit Threshold VCLP VCLN Decreasing VCLN VDCIN l 7 10 13 mV IBDH Back Drive Current Limit Threshold H...

Page 5: ...to DCOUT 6V From DCOUT VGON to DCOUT 1 5V 15 8 60 20 μs μs PWM Flyback Converter VOHF CHGFET DCHFET High ICHGFET IDCHFET 1mA 4 5 4 75 5 25 V VOLF CHGFET DCHFET Low ICHGFET IDCHFET 1mA 50 mV VOLFX CHGFET DCHFET in Shutdown and Backup Modes VDCIN VDCDIV VDCOUT 0V Shutdown Mode VDCIN VDCDIV 0V Backup Mode ICHGFET IDCHFET 1μA 100 mV tR tF CHGFET DCHFET Transition Times Rise Time Fall Time CLOAD 1 6nF ...

Page 6: ... mode The internal clock is running and the SMBus is functional Note 5 Combined current of CSP CSN and BAT pins set to VBAT with no application load Note 6 CTH is deﬁned as the sum of capacitance on THA THB SafetySignal Note 7 Does not include tolerance of current sense or current programming resistors Note 8 Given as a per cell voltage referred to the BAT pin VBAT number of series cells Note 9 Re...

Page 7: ... 1 5 1 0 0 5 0 4110 G03 0 5 10 15 20 TYPICAL PERFORMANCE CHARACTERISTICS Typical CHGFET and DCHFET Waveforms Output Charging Characteristics Showing Constant Current and Constant Voltage Operation Supply Current vs DCIN Voltage in Idle Mode Battery Leakage in Idle Mode IBIDL Battery Current in Backup Mode IBBU Battery Leakage in Shutdown Mode vs Battery Voltage Charging Efﬁciency Power Loss 12VIN ...

Page 8: ...ven input outputportorasabatterychargestatusoutput CHGb withanopen drainN MOSFETthatisassertedlowwhenany smart battery or Li Ion battery is in any phase of charging or when lead acid battery charge current is C x where x C ICHG 5 See C x Charge Termination section for more details If the No SMBus option is selected with the SELA pin the GPIO1 pin defaults as battery charge status Refer to Table 5a...

Page 9: ...stor See description of operation for more detail The maxi mum allowed combined capacitance on THA THB and SafetySignal is 1nF For lead acid battery applications the maximum capacitance on the THA pin is 50pF THB Pin 21 SafetySignal Force Sense Pin to Smart Battery and Sense Pin to Lead Acid Battery Thermistor See description of operation for more detail The maxi mum allowed combined capacitance o...

Page 10: ...y charging Provides synchronous rectiﬁcation during low loss calibration mode VDD Pin 34 Bypass Capacitor Connection for Internal VDD Regulator Bypass at pin with 100nF low ESR capaci tor to GND BATID Pin 35 Drives the Gate of the Battery P MOSFET Ideal Diode Controls low loss ideal diode between the battery and backup load when in backup mode When not in backup mode the P MOSFET is turned off to ...

Page 11: ...WITCH NUMBER OF CELLS CURRENT SELECTION PROGRAMMING CURRENT PRECISION VOLTAGE DIVIDER VDD REGULATOR EA 10 CA OSC 1 220 38 INID 1 DCIN 39 GND 34 VDD 3 CLP 2 CLN 5 DCDIV 17 VREF 16 VCHG 15 VCAL 14 VDIS 30 SELC 19 TYPE 6 SHDN 7 SDA 8 SCL 12 SELA 20 THA 21 THB 10 GPIO2 9 GPIO1 11 GPIO3 13 ACPb 4 ACPDLY 18 TIMER 28 SGND 29 ISENSE 32 DCHFET 33 CHGFET 25 ITH 23 ICAL 24 ICHG 22 IPCC 26 CSP 27 CSN 31 BAT 3...

Page 12: ...an energized battery installed at the factory eliminating battery installation at the site The LTC4110 supports optional control and monitoring of all activities by a host including faults over the industry standard SMBus which is a variation of the I2C bus However no host is required as the LTC4110 is fully functional in a standalone mode Combining all these functions into a single IC reduces cir...

Page 13: ...tect the battery from excessive discharge If the cell voltage drops below the value programmed by the VDIS pin Li Ion default 2 75V cell NiMH NiCd default 0 95V cell lead acid default 1 93V cell the battery P MOSFETs are rapidly turned off and the battery is dis connected from the load If DCIN is above UVLO the load and the LTC4110 will be powered from the supply input If DCIN is below UVLO the LT...

Page 14: ...hreshold and overvoltage threshold will track proportionally The charge cycle begins when the supply input is present as sensed by the DCDIV pin and DCIN above UVLO the battery cell voltage is below the auto recharge threshold 95 of the programmed ﬂoat voltage see VAR thermis tor temperature is within ideal limits COLD under range see SafetySignal Decoder section or is optioned out and the registe...

Page 15: ...argeStatus ICHG or IPPC On CHG_FLT F Timers resume 10 Or Or Or Or DCDIV pin F RES_OR T Bat Removed See ChargeStatus SHDN pin T VUVD T POR_RESET T See ChargeMode ICHG or IPPC Off All Timers Reset ALARM_INHIBITED F CHG_FLT F CHG F CHARGE_INHIBITED F 11 Or VAR T AutoRestart ChargingVoltage ChargingCurrent 0 The battery needs another charge cycle or Smart Battery has requested to start another cycle 1...

Page 16: ... ideal battery temperature When a thermistor is not used the resistor circuit must be routed through the battery connector if battery presence detection is required After a charge cycle has ended without fault the charge cycle is automatically restarted if the average battery cell voltage falls below the auto recharge threshold At any time charging can be forced to stop by pulling the SHDN pin hig...

Page 17: ...rgeStatus ICHG or IPPC Off CHG_FLT T Timer Paused 9 RES_HOT F See ChargeStatus ICHG or IPPC On CHG_FLT F Timer Resume 10 Or Or Or Or DCDIV pin F RES_OR T Bat Removed See ChargeStatus SHDN pin T VUVD T POR_RESET T See ChargeMode ICHG or IPPC Off All Timers Reset CHG_FLT F CHG F ALARM_INHIBITED F CHARGE_INHIBITED F 11 VBOV T Battery Overvoltage PWM stopped Timers remain running 12 VBOV F PWM restart...

Page 18: ... ALARM_INHIBITED becomes set in the ChargerStatus register The state machine will go to the SMBus OFF state CHARGE_INHIBIT is set in the BBuControl register Charge is stopped however the wake up timer is not paused Clearing CHARGE_INHIBIT will enable the LTC4110 to resume charging There is insufﬁcient DCIN voltage to charge the battery as determined by the internal UVLO This causes the statemachin...

Page 19: ... DCDIV VAC VACH and DCIN UVLO ThefollowingconditionswillaffecttheSMBusbulkcharge state as speciﬁed below OPERATION The ChargeCurrent AND ChargeVoltage registers have not been written for tTIMEOUT Charge is stopped and the LTC4110 enters the SMBus OFF state The SafetySignal is registering RES_OR Charge is stopped and the LTC4110 enters the reset state The SafetySignal is registering RES_HOT Charge ...

Page 20: ...ammed ﬂoat voltage during any stage of charge the chargerpausesuntilthevoltagedropsbelowthehysteresis VBOVH No fault is indicated An optional external NTC thermistor network can be used to provide an adjustable negative TC for the ﬂoat voltage monitor battery temperature and to detect battery pres ence If the thermistor value indicates a hot temperature voltagefallingtoVHOTonTHBpin chargecurrentis...

Page 21: ... the supply voltage to unsafe levels should the Figure 5 SLA Charge State Diagram Does Not Include Calibration 4110 F05 PWM STOPPED BATTERY OVP STOP OVERTEMPERATURE ANY CHARGE STATE RESUME CHARGE STATE 8 6 7 5 3 1 9 ANY CHARGE STATE 4 RESET STOP 2 CHARGE Logic Event T True F False Notes Notes and or Actions T True F False 1 RES_OR F DCDIV pin T SHDN pin F CHARGE_INHIBITED F CHG_FLT F ICHG On CHG T...

Page 22: ...r range cold or ideal charge mode is automatically entered to begin recharging the battery Calibration can be restarted by clearing the CAL_FLT bit and sending another CAL_START command An open thermistor over range indicates absence of a battery Todefeatthetemperaturemonitoringfunction re placethethermistorwitharesistortoindicateidealbattery temperature When a thermistor is not used the resistor ...

Page 23: ...DIV pin T SHDN pin F CAL_FLT F CAL_START T CAL_COMPLETE F Calibration started while in Reset Idle or Cold Power Up 2 RES_OR F DCDIV pin T SHDN pin F CAL_FLT F CAL_START T ICHG or IPPC Off All Timers Reset CAL_COMPLETE F Calibration was initiated while in any mode other than Reset 3 Calibration Automatically Started ICAL ON CAL_ON T 4 VBAT VCAL Battery has reached Discharge ICAL Off CAL_ON F CAL_CO...

Page 24: ...d The actual x value depends on the programmed charging cur rent and the C rate of the battery x C ICHG 5 OPERATION Figure 9 LTC4110 PWM Engine In shutdown charge calibration and backup modes are inhibited all registers are set to their default states with exception of the backup fault bit register the internal timer is reset and oscillator disabled the status pins ACPb GPIO1 GPIO2 and GPIO3 are a...

Page 25: ...ator and two comparators The state machine successively samples the SafetySignal value starting with the RES_OR RES_COLD threshold then RES_C0LD RES_IDEAL threshold RES_IDEAL RES_HOT threshold and ﬁnally the RES_HOT RES_UR threshold Once the SafetySignal range is determined the lower value thresholds are not sampled The SafetySignal decoderblockusesthepreviouslydeterminedSafetySignal valuetoprovid...

Page 26: ...either CHG_STATE_0 or CHG_STATE_1 is set to one C xb is asserted low signal when C x state in the charge cycle is reached This status signal is only available if the TYPE pin is set to SLA mode and replaces the CHGb status output BKUP_FLTb is asserted low when the BKUP_FLT bit is set tooneintheBBuStatus register BKUP_FLTisastickybit thatisdesignedtobeclearedprimarilythroughthesetting oftheBUFLT_RS...

Page 27: ...tate at any time The LTC4110 command set is interpreted by the SMBus interface and passed onto the charger controller block as control signals or updates to internal registers Smart battery charge commands are Table 5c GPIO2 Modes HOST PROGRAMMED BIT SETTINGS GPIO_2 MODE DATA NOTE GPIO_2_EN GPIO_2_OUT GPIO_2_BUFLT 0 0 0 Digital Input Input Data GPIO_2_IN 1 X 1 Status Output BKUP_FLTb With Pull Up ...

Page 28: ...iple channel SMBus multiplexer ICs such as the LTC4305 and LTC4306 to help implement the required isolation Furthermore if a given SMBus is high in SMBus device count or long in length you may want to consider using SMBus accelerators The above ICs listed support that option If the SMBus is not used or to force all GPIOs to status mode upon power up connect SELA to a typically 0 5 VREF voltage fro...

Page 29: ...ES_OR for SLA RES_OR The RES_OR bit is set when the SafetySignal resistance value is above 100kΩ 114kΩ for SLA typical The SafetySiganl indicates an open circuit LEVEL 3 LEVEL 2 The LTC4110 always reports itself as a Level 2 Smart Battery Charger CHARGE_INHIBITED Indicates charge inhibited is enabled when set to a one This is a duplicate of the CHARGE_INHIBIT bit in the BBuStatus register Charging...

Page 30: ...ated early CHG_STATE_0 Combined with CHG_STATE_1 indicates phase of charging 00 Off 01 precharge 10 bulk charge 11 top off charge CHG_STATE_1 See CHG_STATE_0 CHARGE_INHIBITED Indicates charge inhibited is enabled when set to a one This as a duplicate of CHARGE_INHIBIT bit in the ChargerStatus register BBuControl Write Only The SMBus host uses this command to control the LTC4110 CAL_START Set to on...

Page 31: ...l faults and timers in charge and forces the ChargingCurrent and ChargingVoltage to zero values Clears Alarm_Warning register Does not affect BBuControl register Bit clears to zero automatically after the command is executed default cleared to zero no reset POR_RESET Resets LTC4110 to power on default values Setting the bit to a one will activate POR_RESET POR_RESET performs a total chip wide rese...

Page 32: ...MP_ALARM TERMINATE_DISCHARGE_ALARM RESERVED REMAINING_CAPACITY_ALARM REMAINING_TIME_ALRAM INITIALIZED DISCHARGING FULLY_CHARGED FULLY_DISCHARGED ERROR Write Permitted Values 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 BBuStatus 7 b0001_ 001 8 h3D Status CAL__ON CAL_COMPLETE BKUP_ON Reserved Reserved GPIO_1_IN GPIO_2_IN GPIO_3_IN Reserved CHG_FLT BKUP_FLT CAL_FLT CHG_STATE_0 CHG_STATE_1 Reserved CHAR...

Page 33: ...to the IC unless in shutdown mode Such action will result in unpredictable behavior from the LTC4110 SUPERCAPS Table 8 shows all of the options with the exception of SuperCaps SuperCaps are supported by using standard Li ionorSLAmodesincombinationwiththeadjustingthe charge voltage with the VCHG pin As far as the LTC4110 is concerned it is still working with a Li ion or SLA bat tery and will follow...

Page 34: ... than 30W 2 5A 12V when full power is drawn the adapter voltage will be pulled down by the constant 30W load until it reaches a lower stable state where the switching regulators can no longer supply full load This situation can be prevented by utilizing the DCDIV resistor divider set higher than the minimum adapter voltage where full power can be achieved APPLICATIONS INFORMATION CALIBRATION MODE ...

Page 35: ...P and CSN pins equals VSNS RCSP1 RCSP2 100mV RCSP1 RCSP2 averysmallRCSP1 RCSP2 value will result in a large current Typically a value between 3k and 30k gives the best performance Figure 12 CSP CSN RC Filter CCSP 330n CCSN 330n RSNS BAT 100mV RCSP2 2k RCSN2 2k RCSP1 1k RCSN1 1k 4110 F12 LTC4110 CA Recommended starting values for the ﬁlter is RCSP1 RCSN1 between 1K and 2K RCSP1 RCSP2 RCSN1 RCSN2 ab...

Page 36: ...etVSNS FET besetto50mV for good efﬁciency and solve for RSNS FET R V I SNS FET SNS FET PRI With an initial value of RSNS FET identiﬁed solve for VSNS FET using the highest value between IPRI CHG or IPRI CAL and see if the calculated value of VSNS FET falls below the upper limits If it is too high you may have to dropthevalueofRSNS FET IfyoucannotmeettheVSNS FET upper or lower limits and or ratio l...

Page 37: ...oltage VBGR 1 220V The resistor divider connected to VREF pin will affect timer see the Programming Charge Time with TIMER and VREF Pins section for more details THERMISTOR FOR LEAD ACID BATTERIES When the TYPE pin is programmed for Lead Acid THA pin will be force to VBGR THB will be used to sense the NTC resistance The value of R1 is given by R1 R0 β 2 T0 β 2 T0 where R0 thermistor resistance Ω a...

Page 38: ...th the backup mode entry threshold and the calibration mode back drive voltage detection threshold VBACKUP R2 R1 1 VBGR VBACKDRIVE VOVP VBGR VBACKUP R2 R1 VBACKUP VBGR 1 where VBACKUP supply voltage when backup starts it should not be programmed to less than 4 5V VBACKDRIVE supplyvoltagewhencalibrationisterminated it should not be programmed to more than 20V VOVP DCDIVpinback drivedetectthresholdi...

Page 39: ...essary voltage divider network from VREF required to get the calculated voltage on these pins respectively It is recommended that one single series resistor divider network from VREF to ground beusedtoobtainallofthepinvoltagesyouneed Itshould be noted that custom values of VCHG would also affect the divider network complexity See Programming Charge Voltage section for more information Connect the ...

Page 40: ...meddelaytimes range from 10ms to 200ms and is set as follows CACPDLY F T s 2 RVREF Ω As an example if RVREF 113k and the desired delay time is 105ms then CTIMER 470nF See tAC in the Electrical Characteristics Table for the tolerance where VCUTOFF adjusted cutoff threshold voltage VCAL VDIS voltage on VCAL or VDIS pin VBGR 1 220V The resistor divider connected to VREF pin will affect timer See the ...

Page 41: ...t comparator threshold in proportion to duty cycle This stabilizes the control loop against subharmonic oscillation The amount of reduction in the currentcomparatorthreshold ΔVISENSE canbecalculated using the following equation ΔVISENSE DUTY CYCLE VSEC 400k RSL To program m m2 R N k R F Lm SL SNSFET 1 400 where N transformer turns ratio NBAT NDCIN RSNS FET sense resistor connected between MOSFET a...

Page 42: ...wer rating is a function of the highest current value between ICHG or ICAL with which the battery will work Plug in the higher of the two into IBAT MAX and solve PR SNSBAT IMAX 2 RSNS BAT Use a sense resistor with a power rating greater than PSNS BAT FLYBACK MOSFET SELECTION The LTC4110 uses two low side N channel switching MOSFETs in its ﬂyback converter These MOSFETs have dual roles An any given...

Page 43: ... VGS VT on resistance RDS ON and QGATE The maximum allowable drain source voltage VDS MAX must be high enough to withstand the maximum drain source voltage seen in the application The gates of these MOSFETs are driven by the INID Input Ideal Diode and BATID Battery Ideal Diode pins The gate turn on voltage VGS is set by the smaller of the PowerPath supply voltage or the internal clamping volt age ...

Page 44: ...s that can help youquicklyﬁndandselecttherighttransformer Thereare manyofftheshelftransformersthatcanbesuccessfullybe used with the LTC4110 Table 10 shows some suggested off the shelf transformers If you want to design a custom transformer optimized for your design Application Note 19 has an example of how to design a Flyback transformer in the Transformer section APPLICATIONS INFORMATION Regardle...

Page 45: ...ery impedance is raised to 2v with a bead or induc tor only 5 of the ripple current will ﬂow in the battery APPLICATIONS INFORMATION Similar techniques may also be applied to minimize EMI from the input leads Diodes Schottky diodes should be placed in parallel with the drain and source of the Flyback MOSFETs This prevents body diode turn on and improves efﬁciency by eliminating loss from reverse r...

Page 46: ...en the LTC4110 and the actual load The characteristics of this regulator should offer high efﬁciency when running from the battery in backup mode to maximize backup time Some regulators may need advance warning when to enter into this mode which can be accomplished by using the LTC4110 s ACPb pin DCIN TO BATTERY TRANSITION CHATTER REMOVAL The LTC4110 is designed to automatically switch the bat ter...

Page 47: ...als 4 Place the snubber connections as close as possible to the circuit after the above layout connections are completed as required Again avoid using vias 5 The layer below the ﬂyback layout should be ground Other Recommendations 6 Optionally use vias to connect power supply sources positive and negative ground connections from other copper layers to the ﬂyback layout Place multiple vias in a tig...

Page 48: ...OAD DESIGN 0 5A BACKDRIVE CURRENT CUTOFF CALIBRATION 1A CHARGE AND CALIBRATION CURRENT ALL RESISTORS ARE 1 UNLESS NOTED OTHERWISE Q1 Si7216DN Q2 Si7445DP Q3 Si7983DP T1 BH510 1019 20μF VERY LOW ESR BATTERY IDEAL DIODE INPUT IDEAL DIODE Q2 TO SYSTEM LOAD TO BACKUP LOAD 12V VCHG VCAL VDIS VDD ICHG ICAL IPCC SELA SELC SDA SCL TYPE DCOUT SUPPLY INPUT 12V NC BATID CHGFET DCHFET ISENSE CSP CSN BAT ITH A...

Page 49: ...LY TIMER VDD ACPb GP101 GP102 GP103 SHDN GND SGND 20μF VERY LOW ESR I2C TO HOST 4110 TA05 LTC4110 0 1μF LOW ESR 0 1μF LOW ESR THB RTHA 1 13k RTHB 54 9k 1 21k 49 9k 8 66k RSNS FET 0 05Ω 0 5W 33Ω 0 5W 5 33Ω 0 5W 5 RSL 3 32k RCL 0 02Ω 1W 3 01k 0 1μF 0 1μF 1k 2k 330nF 1nF 1nF 1k 2k 330nF RSNS BAT 0 1Ω 0 25W NO TIMER HIGH CURRENT BACKUP LOAD DESIGN 0 5A BACKDRIVE CURRENT CUTOFF CALIBRATION 1A CHARGE AN...

Page 50: ...CHGFET DCHFET I SENSE CSP CSN BAT I TH ACPDLY TIMER V DD ACPb GP101 GP102 GP103 SHDN GND SGND 20μF VERY LOW ESR SMB1 SMBUS MULTIPLEXOR HOST I 2 C SMBus LTC4305 LTC4110 0 1μF LOW ESR 0 1μF LOW ESR THB R THA 1 13k R THB 54 9k V CHG V CAL V DIS I CHG I CAL I PCC SELA 1 21k 113k 8 66k R CL 0 02Ω 1W 0 1μF 7HR CHARGE TIME HIGH CURRENT BACKUP LOAD DESIGN 0 5A BACKDRIVE CURRENT CUTOFF 1A CHARGE AND CALIBR...

Page 51: ... MILLIMETERS PIN 1 TOP MARK SEE NOTE 6 37 1 2 38 BOTTOM VIEW EXPOSED PAD 5 50 REF 5 15 0 10 7 00 p 0 10 0 75 p 0 05 R 0 125 TYP R 0 10 TYP 0 25 p 0 05 UH QFN REF C 1107 0 50 BSC 0 200 REF 0 00 0 05 RECOMMENDED SOLDER PAD LAYOUT APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 3 00 REF 3 15 0 10 0 40 p0 10 0 70 p 0 05 0 50 BSC 5 5 REF 3 00 REF 3 15 0 05 4 10 p 0 05 5 50 p 0 05 5 15 0 05 6 10 p 0 05...

Page 52: ... 3 5V to 36V AC DC Adapter Voltage Range MSOP 8 Package LTC4416 LTC4416 1 Dual Low Loss PowerPath Controllers Drives Large PFETs Low Loss Replacement for Power Supply ORing Diodes Operation to 36V Programmable Autonomous Switching ThinSot is a Trademark of Linear Technology Corporation RSNS BAT 0 1Ω 0 25W DCIN INID CLN CLP DCDIV RTHA 1 13k THA THB VREF 10k NTC I2C TO HOST 0 1μF LOW ESR 22μF VERY L...

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