Linear Technology DC1974 Series Demo Manual Download Page 7

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dc1974f

DEMO MANUAL DC1974

Lane Alignment Sequence

 – Enables or disables the lane 

alignment sequence.

n

  Enabled (Default) – Lane  alignment  sequence  is 

enabled.

n

  Disabled - Lane alignment sequence is disabled.

Lane Alignment Monitor

 – Enables or disables the lane 

monitor sequence.

n

  Enabled (Default) – Lane alignment monitor sequence 

is enabled.

n

  Disabled  –  Lane  alignment  monitor  sequence  is 

disabled.

Frame Alignment Monitor

 – Enables or disables the Frame 

monitor sequence

n

  Enabled (Default) – Frame alignment monitor se-

quence is enabled.

n

  Disabled – Frame alignment monitor sequence is 

disabled.

Reset Dividers (Subclass 1 or 2 Only)

 – Enables or dis-

ables SYSREF reset of dividers.

n

  Enabled (Default) – Subclass 1 – Enables the SYSREF 

reset of dividers. Subclass 2 – Enables SYNC~ reset 

of dividers.

n

  Disabled – Subclass 1 – Disables the SYSREF reset 

of dividers. Subclass 2 – Disables SYNC~ reset of 

dividers. 

Scrambling

 – Enables or disables the scrambling of the 

output data.

n

  Disabled (Default) – Scrambling is disabled.

n

  Enabled – Scrambling is enabled.

Alert Mode De-arm Length (Subclass 1 Only)

 – Selects 

the de-arming length in multiframe periods to trigger the 

alert in subclass 1. Valid values are 1 to 8.

Alert Mode (Subclass 1 Only)

 – Enables or disables the 

alert mode.

n

  Disabled (Default) – Alert mode is disabled.

n

  Enabled – Alert mode is enabled.

TX Sync

 – Enables or disables Transmitter induced syn-

chronization.

n

  Disabled (Default) – Transmitter induced synchro-

nization is disabled.

n

  Enabled - Transmitter  induced  synchronization 

is enabled.

Test Pattern

 – Selects the data presented at the output 

of the ADC

  Normal ADC Data (Default)

 – The data that is sampled 

by the input of the ADC

  K28.5 Pattern

 – A repeating SYNC comma.

  K28.7 Pattern

 – 1111100000.

  D21.5 Pattern

 – 1010101010.

  PRBS15 Pattern

 – A Pseudorandom bit sequence pat-

tern described by 1 + x

14

 + x

15

.

  Lane Alignment Sequence

 – The lane alignment se-

quence is transmitted according to tables 3a to 3h from 

the datasheet.

  Test Samples Sequence

 – The test samples are repeat-

edly transmitted according to tables 4a to 4b from the  

datasheet.

  Modified RPAT Pattern

 – A modified RPAT pattern as 

described in IEEE Std. 802.3-2008 Annex 48A.

CML  Output  Magnitude

  –  Magnitude  of  the  CML  out-

put signals.
Value selections are:
 10mA (250mV) Default
 12mA (300mV) 
 14mA (350mV) 
 16mA (400mV) 
Once the desired settings are selected hit OK and PScope 

will automatically update the register of the device on the 

DC1974 demo board.

SOFTWARE

Summary of Contents for DC1974 Series

Page 1: ...proper input networks for dif ferent input frequencies Design files for this circuit board are available at http www linear com demo DC1974 DC1974 VARIANTS ADC PART NUMBER RESOLUTION Bit MAXIMUM SAMP...

Page 2: ...ation with the host computer Follow the instructions in Appendix A for the Xilinx KC705 based system Verilog codemaybedownloadedfromtherespectiveADClanding page www linear com LTC2123 CHANNEL 1 SINGLE...

Page 3: ...or testing purposes only In the default configuration these SMAs are not used J9 and J10 FPGA_CLK This is an optional clock input port for the FPGA It is used for testing purposes only In the default...

Page 4: ...he DC1974 is single ended there is a transformer on the board that translates the single ended signal to a differential signal to drive the ADC ANALOG INPUT NETWORK In almost all cases off board filte...

Page 5: ...configure PScope Underthe Configure menu goto ADCConfiguration Check the Config Manually box and use the following configuration options shown in Figure 2 Manual Configuration settings Bits 14 Alignm...

Page 6: ...l to the device clock or device clock twice the sample rate n Off Default DEVCLK is equal to the sample rate n On DEVCLK is twice the sample rate Overflow Enables or disables the overflow bit in the o...

Page 7: ...riods to trigger the alert in subclass 1 Valid values are 1 to 8 Alert Mode Subclass 1 Only Enables or disables the alert mode n Disabled Default Alert mode is disabled n Enabled Alert mode is enabled...

Page 8: ...chnology will need to be configured as described in the Alternate FPGA Configuration section below 4 Apply power encode clock and analog input signals to the DC1974 board 5 VerifythatPScopesoftwareisi...

Page 9: ...CONNECT DC2159 TO PC 1 ASSEMBLE BOARDS 4 POWER UP DC1974 TURN ON CLOCK AND ANALOG INPUTS 3 CONFIGURE FPGA VIA JTAG IF NECESSARY THEN REMOVE USB CABLE 2 POWER UP KC705 dc1974 F05 Figure 5 KC705 Based D...

Page 10: ...16 1 L2 IND FERRITE BEAD 33 1206 MURATA BLM31PG330SN1L 17 0 L3 RES 1206 OPT 18 2 R1 R59 RES CHIP 3 01k 1 16W 1 0402 VISHAY CRCW04023K01FKED 19 1 R2 RES CHIP 10k 1 16W 1 0402 VISHAY CRCW040210K0FKED 20...

Page 11: ...TALL 40 0 MH1 MH2 STAND OFF ALUM M3 THREAD 5 0 HEX 4 40X1 KEYSTONE 24438 DO NOT INSTALL 41 2 STENCILS STENCILS TOP BOTTOM STENCIL DC1974A 3 DC1974A A Required Circuit Components 1 1 DC1974A GENERAL BO...

Page 12: ...NTACT LINEAR TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND SCHEMATIC SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS SCALE NONE www linear com 3...

Page 13: ...E25 GND E26 HB09_P E27 HB09_N E28 GND E29 HB13_P E30 HB13_N E31 GND E32 HB21_P E33 HB21_N E34 GND E35 HB20_P E36 HB20_N E37 GND E38 VADJ E39 GND E40 SCK SCK J13A SEAM 10X40PIN J13A SEAM 10X40PIN GND...

Page 14: ...RY INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE EXCEPT TO THE EXTENT OF THIS INDEMNITY NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT SPECIAL INCIDENTAL...

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