4
dc1974f
DEMO MANUAL DC1974
If a Kintex 7 FPGA board is used to acquire data from
the DC1974, the Kintex 7 FPGA board must FIRST be
powered BEFORE applying 4V to 6V across the pins marked
“V+” and “GND” on the DC1974. For more information
about the Kintex 7 board, please see the demo manual at
www.xilinx.com. The DC1974 requires at least 4V for proper
operation. Regulators on the board produce the voltages
required for the ADC and the required logic devices. The
DC1974 requires up to 700mA. The DC1974 should not be
removed or connected to the Kintex 7 FPGA board while
power is applied.
The DC2159 should also be connected to the Kintex 7
board and the supplied mini USB cable should be con-
nected to the DC2159. The Kintex 7 board should be
powered on BEFORE the mini USB connector is connected
to the DC2159. See Figure 5 in Appendix A.
APPLYING POWER AND SIGNALS TO THE DC1974 DEMONSTRATION CIRCUIT
Apply the analog input signal of interest to the SMA con-
nector on the DC1974 board marked J1 or J2. In the default
setup, the DC1974 has a single SMA input that is meant
to be driven with a 50Ω source. The DC1974 is populated
with an input network that has 50Ω characteristic imped-
ance over a wide frequency range. This can be modified
to produce different frequency responses as needed. Al-
though the input of the DC1974 is single-ended, there is a
transformer on the board that translates the single-ended
signal to a differential signal to drive the ADC.
ANALOG INPUT NETWORK
In almost all cases, off board filters with good return loss
will be required on the analog input of the DC1974 to
produce data sheet SNR.
The off board filter should be located close to the input
of the demo board to avoid reflections from impedance
discontinuities at the driven end of a long transmission line.
Most filters do not present 50Ω outside the passband. In
some cases, 3dB to 10dB pads may be required to make
the filter look more like 50Ω to obtain low distortion.
Apply an encode clock to the SMA connector on the DC1974
marked J3. By default, the DC1974 is configured to have
a single-ended clock input. Although the clock input of
the DC1974 is single-ended, there is a transformer on
the board that translates the single-ended signal to a dif-
ferential signal to drive the ADC.
For the best noise performance, the encode input must
be driven with a very low jitter signal generator source.
The amplitude should be as large as possible up to 2V
PP
or 10dBm.
The DC1974 is designed to accept single-ended signals
by default. To modify the DC1974 to accept a differential
signal, remove C33, R44, R45 and R46. Populate R49,
R43, R48 and R47 with 0Ω resistors. Drive the demo
board with a differential signal on J3 and J4. These SMAs
are positioned 0.5" apart to accommodate LTC differential
clock boards.
ENCODE CLOCK
