Linear Technology DC1974 Series Demo Manual Download Page 10

10

dc1974f

DEMO MANUAL DC1974

PARTS LIST

ITEM QTY REFERENCE

PART DESCRIPTION

MANUFACTURER/PART #

Required Circuit Components

1

2

C1, C2

CAP., X5R, 1µF, 10V, 10%, 0402

AVX, 0402ZD105KAT2A

2

1

C3

CAP., TANT, 100µF, 10V, 10%, 6032

AVX, TAJW107K010RNJ

3

1

C4

CAP., X7R, 47µF,10V, 10%, 1210

MURATA, GRM32ER71A476KE15L

4

4

C5, C11, C25, C26

CAP., X5R, 2.2µF, 10V, 20%, 0603

AVX, 0603ZD225MAT2A 

5

7

C6, C33-C35, C50-C52

CAP., X7R, 0.01µF, 16V, 10%, 0402

AVX, 0402YC103KAT2A

6

1

C7

CAP., X5R, 10µF, 6.3V, 20%, 0805

AVX, 08056D106MAT2A

7

22

C10, C12-C24, C27-C32, C41, C53 CAP., X5R, 0.1µF, 10V, 10%, 0402

AVX, 0402ZD104KAT2A

8

4

C37, C38, C39, C40

CAP., C0G, 47pF, 16V, 10%, 0402

AVX, 0402YA470KAT2A

9

8

C42-C49

CAP., X7R, 1000pF, 50V, 10%, 0402

AVX, 04025C102KAT2A 

10

4

E1, E2, E3, E4

TESTPOINT, TURRET, 0.094"

MILL-MAX, 2501-2-00-80-00-00-07-0

11

2

JP1, JP2

HEADER, HD1X3-079

SULLINS, NRPN031PAEN-RC

12

10

J1-J6, J9-J12

CONN., SMA 50Ω, EDGE-LAUNCH

EF JOHNSON, 142-0701-851

13

0

J7, J8 (OPT)

CONN., SMA 50Ω, EDGE-LAUNCH

EF JOHNSON, 142-0701-851

14

1

J13

CONN., BGA 40X10

SAMTEC, SEAM-40-02.0-S-10-2-A-K-TR

15

1

L1

RES., CHIP, 0Ω, 1206

VISHAY, CRCW12060000Z0EA

16

1

L2

IND., FERRITE BEAD, 33Ω, 1206

MURATA, BLM31PG330SN1L

17

0

L3

RES., 1206

OPT

18

2

R1,R59

RES., CHIP, 3.01k, 1/16W, 1%, 0402

VISHAY, CRCW04023K01FKED

19

1

R2

RES., CHIP, 10k, 1/16W, 1%, 0402

VISHAY, CRCW040210K0FKED

20

1

R4

RES., CHIP, 182k, 1/16W, 1%, 0402

VISHAY, CRCW0402182KFKED

21

4

R5, R24, R25, R58

RES., CHIP, 1k, 1/16W, 1%, 0402

NIC, NRC04F1001TRF

22

10

R6-R11, R32-R35

RES., CHIP, 24.9Ω, 1/16W, 1%, 0402

VISHAY, CRCW040224R9FKED

23

11

R12, R13, R15, R16, R18, R39,  

R40, R44, R45, R46, R57

RES., CHIP, 0Ω, 1/16W, 0402

NIC, NRC04Z0TRF

24

5

R14, R17, R41, R56, R61

RES., CHIP, 100Ω, 1/16W, 1%, 0402

NIC, NRC04F1000TRF

25

0

R19-R23, R42, R43, R48-R53,  

R54, R55, R60

RES., 0402

OPT

26

2

R26, R29

RES., CHIP, 20Ω, 1/16W, 1%, 0402

NIC, NRC04F20R0TRF

27

2

R27, R28

RES., CHIP, 49.9Ω, 1/16W, 1%, 0402

VISHAY, CRCW040249R9FKED

28

2

R30, R31

RES., CHIP, 300Ω, 1/16W, 1%, 0402

NIC, NRC04F3000TRF

29

3

R36, R37,R38

RES., CHIP, 4.99k, 1/16W, 1%, 0402

VISHAY, CRCW04024K99FKED

30

5

R47, R62,R63,R64,R65

RES., CHIP, 4.99Ω, 1/16W, 1%, 0402

NIC, NRC04F4R99TRF

31

2

R66, R67

RES., CHIP, 100Ω, 1/20W, 1%, 0201

NIC, NRC02F1000TRF

32

3

T1, T2, T3

XFMR., MABA-007159-000000

M/A-COM, MABA-007159-000000

33

1

U2

I.C., LT3080EDD#PBF, DFN 3X3

LINEAR TECH., LT3080EDD#PBF

34

1

U3

I.C., LT1763CDE-3.3#PBF, DFN12DE-4X3

LINEAR TECH., LT1763CDE-3.3#PBF

35

1

U6

I.C. EEPROM 32KBIT 400KHz, TSSOP8

MICROCHIP, 24LC32A-I/ST

Summary of Contents for DC1974 Series

Page 1: ...proper input networks for dif ferent input frequencies Design files for this circuit board are available at http www linear com demo DC1974 DC1974 VARIANTS ADC PART NUMBER RESOLUTION Bit MAXIMUM SAMP...

Page 2: ...ation with the host computer Follow the instructions in Appendix A for the Xilinx KC705 based system Verilog codemaybedownloadedfromtherespectiveADClanding page www linear com LTC2123 CHANNEL 1 SINGLE...

Page 3: ...or testing purposes only In the default configuration these SMAs are not used J9 and J10 FPGA_CLK This is an optional clock input port for the FPGA It is used for testing purposes only In the default...

Page 4: ...he DC1974 is single ended there is a transformer on the board that translates the single ended signal to a differential signal to drive the ADC ANALOG INPUT NETWORK In almost all cases off board filte...

Page 5: ...configure PScope Underthe Configure menu goto ADCConfiguration Check the Config Manually box and use the following configuration options shown in Figure 2 Manual Configuration settings Bits 14 Alignm...

Page 6: ...l to the device clock or device clock twice the sample rate n Off Default DEVCLK is equal to the sample rate n On DEVCLK is twice the sample rate Overflow Enables or disables the overflow bit in the o...

Page 7: ...riods to trigger the alert in subclass 1 Valid values are 1 to 8 Alert Mode Subclass 1 Only Enables or disables the alert mode n Disabled Default Alert mode is disabled n Enabled Alert mode is enabled...

Page 8: ...chnology will need to be configured as described in the Alternate FPGA Configuration section below 4 Apply power encode clock and analog input signals to the DC1974 board 5 VerifythatPScopesoftwareisi...

Page 9: ...CONNECT DC2159 TO PC 1 ASSEMBLE BOARDS 4 POWER UP DC1974 TURN ON CLOCK AND ANALOG INPUTS 3 CONFIGURE FPGA VIA JTAG IF NECESSARY THEN REMOVE USB CABLE 2 POWER UP KC705 dc1974 F05 Figure 5 KC705 Based D...

Page 10: ...16 1 L2 IND FERRITE BEAD 33 1206 MURATA BLM31PG330SN1L 17 0 L3 RES 1206 OPT 18 2 R1 R59 RES CHIP 3 01k 1 16W 1 0402 VISHAY CRCW04023K01FKED 19 1 R2 RES CHIP 10k 1 16W 1 0402 VISHAY CRCW040210K0FKED 20...

Page 11: ...TALL 40 0 MH1 MH2 STAND OFF ALUM M3 THREAD 5 0 HEX 4 40X1 KEYSTONE 24438 DO NOT INSTALL 41 2 STENCILS STENCILS TOP BOTTOM STENCIL DC1974A 3 DC1974A A Required Circuit Components 1 1 DC1974A GENERAL BO...

Page 12: ...NTACT LINEAR TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND SCHEMATIC SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS SCALE NONE www linear com 3...

Page 13: ...E25 GND E26 HB09_P E27 HB09_N E28 GND E29 HB13_P E30 HB13_N E31 GND E32 HB21_P E33 HB21_N E34 GND E35 HB20_P E36 HB20_N E37 GND E38 VADJ E39 GND E40 SCK SCK J13A SEAM 10X40PIN J13A SEAM 10X40PIN GND...

Page 14: ...RY INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE EXCEPT TO THE EXTENT OF THIS INDEMNITY NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT SPECIAL INCIDENTAL...

Reviews: