Linear Technology DC1974 Series Demo Manual Download Page 13

13

dc1974f

DEMO MANUAL DC1974

Information  furnished  by  Linear  Technology  Corporation  is  believed  to  be  accurate  and  reliable.  

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

SCHEMATIC DIAGRAM

5

5

4

4

3

3

2

2

1

1

D

D

C

C

B

B

A

A

EEPROM

WP

PROG

CS_FMC

SCL SDA

SCK_FMC

SDI_FMC

SDO_FMC

3P3VAUX

VDD

+3.3V

CS

SDO

SDI

SCK

CMLA2_P CMLA2_N

CMLB1_N

CMLB1_P

CMLB2_N

CMLB2_P

CMLA1_P CMLA1_N

SYNC_P SYNC_N

OF+ OF-

FPGA_CLK_P FPGA_CLK_N

SIZE

DATE:

IC NO.

REV.

SHEET

OF

TITLE:

APPROVALS

PCB DES.

APP ENG.

TECHNOLOGY

Fax: (408)434-0507

Milpitas, CA 95035 Phone: (408)432-1900

1630 McCarthy Blvd.

LTC Confidential-For Customer Use Only

CUSTOMER NOTICE

LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS; HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL APPLICATION.  COMPONENT SUBSTITUTION AND PRINTED CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT PERFORMANCE OR RELIABILITY.  CONTACT LINEAR TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE.

THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND

SCHEMATIC

SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS.

SCALE = NONE

www.linear.com

3

DEMO CIRCUIT 1974A

Thursday, July 31, 2014

2

2

N/A

LTC212XIUK FAMILY

KIM T.

CLARENCE M.

DUAL 14-BIT HIGH SPEED ADC WITH JESD204B SERIAL OUTPUTS

SIZE

DATE:

IC NO.

REV.

SHEET

OF

TITLE:

APPROVALS

PCB DES.

APP ENG.

TECHNOLOGY

Fax: (408)434-0507

Milpitas, CA 95035 Phone: (408)432-1900

1630 McCarthy Blvd.

LTC Confidential-For Customer Use Only

CUSTOMER NOTICE

LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS; HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL APPLICATION.  COMPONENT SUBSTITUTION AND PRINTED CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT PERFORMANCE OR RELIABILITY.  CONTACT LINEAR TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE.

THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND

SCHEMATIC

SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS.

SCALE = NONE

www.linear.com

3

DEMO CIRCUIT 1974A

Thursday, July 31, 2014

2

2

N/A

LTC212XIUK FAMILY

KIM T.

CLARENCE M.

DUAL 14-BIT HIGH SPEED ADC WITH JESD204B SERIAL OUTPUTS

SIZE

DATE:

IC NO.

REV.

SHEET

OF

TITLE:

APPROVALS

PCB DES.

APP ENG.

TECHNOLOGY

Fax: (408)434-0507

Milpitas, CA 95035 Phone: (408)432-1900

1630 McCarthy Blvd.

LTC Confidential-For Customer Use Only

CUSTOMER NOTICE

LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS; HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL APPLICATION.  COMPONENT SUBSTITUTION AND PRINTED CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT PERFORMANCE OR RELIABILITY.  CONTACT LINEAR TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE.

THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND

SCHEMATIC

SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS.

SCALE = NONE

www.linear.com

3

DEMO CIRCUIT 1974A

Thursday, July 31, 2014

2

2

N/A

LTC212XIUK FAMILY

KIM T.

CLARENCE M.

DUAL 14-BIT HIGH SPEED ADC WITH JESD204B SERIAL OUTPUTS

R32 24.9

R32 24.9

J12

FPGA_SYS_REF_N

SMA

J12

FPGA_SYS_REF_N

SMA

J13J

SEAM-10X40PIN

J13J

SEAM-10X40PIN

GND

J1

CLK1_C2M_P

J2

CLK1_C2M_N

J3

GND

J4

GND

J5

HA03_P

J6

HA03_N

J7

GND

J8

HA07_P

J9

HA07_N

J10

GND

J11

HA11_P

J12

HA11_N

J13

GND

J14

HA14_P

J15

HA14_N

J16

GND

J17

HA18_P

J18

HA18_N

J19

GND

J20

HA22_P

J21

HA22_N

J22

GND

J23

HB01_P

J24

HB01_N

J25

GND

J26

PB07_P

J27

HB07_N

J28

GND

J29

HB11_P

J30

HB11_N

J31

GND

J32

HB15_P

J33

HB15_N

J34

GND

J35

HB18_P

J36

HB18_N

J37

GND

J38

VIO_B_M2C

J39

GND

J40

R33 24.9

R33 24.9

R37 4.99KR374.99K

J13E

SEAM-10X40PIN

J13E

SEAM-10X40PIN

GND

E1

HA01_P_CC

E2

HA01_N_CC

E3

GND

E4

GND

E5

HA05_P

E6

HA05_N

E7

GND

E8

HA09_P

E9

HA09_N

E10

GND

E11

HA13_P

E12

HA13_N

E13

GND

E14

HA16_P

E15

HA16_N

E16

GND

E17

HA20_P

E18

HA20_N

E19

GND

E20

HB03_P

E21

HB03_N

E22

GND

E23

HB05_P

E24

HB05_N

E25

GND

E26

HB09_P

E27

HB09_N

E28

GND

E29

HB13_P

E30

HB13_N

E31

GND

E32

HB21_P

E33

HB21_N

E34

GND

E35

HB20_P

E36

HB20_N

E37

GND

E38

VADJ

E39

GND

E40

SCKSCK

J13A

SEAM-10X40PIN

J13A

SEAM-10X40PIN

GND

A1

DP1_M2C_P

A2

DP1_M2C_N

A3

GND

A4

GND

A5

DP2_M2C_P

A6

DP2_M2C_N

A7

GND

A8

GND

A9

DP3_M2C_P

A10

DP3_M2C_N

A11

GND

A12

GND

A13

DP4_M2C_P

A14

DP4_M2C_N

A15

GND

A16

GND

A17

DP5_M2C_P

A18

DP5_M2C_N

A19

GND

A20

GND

A21

DP1_C2M_P

A22

DP1_C2M_N

A23

GND

A24

GND

A25

DP2_C2M_P

A26

DP2_C2M_N

A27

GND

A28

GND

A29

DP3_C2M_P

A30

DP3_C2M_N

A31

GND

A32

GND

A33

DP4_C2M_P

A34

DP4_C2M_N

A35

GND

A36

GND

A37

DP5_C2M_P

A38

DP5_C2M_N

A39

GND

A40

C40 47pF

C40 47pF

J7

FPGA_GBT_REF_P

SMA

OPT

J7

FPGA_GBT_REF_P

SMA

OPT

C39 47pF

C39 47pF

J13K

SEAM-10X40PIN

J13K

SEAM-10X40PIN

VREF_B_M2C

K1

GND

K2

GND

K3

CLK1_M2C_P

K4

CLK1_M2C_N

K5

GND

K6

HA02_P

K7

HA02_N

K8

GND

K9

HA06_P

K10

HA06_N

K11

GND

K12

HA10_P

K13

HA10_N

K14

GND

K15

HA17_P_CC

K16

HA17_N_CC

K17

GND

K18

HA21_P

K19

HA21_N

K20

GND

K21

HA23_P

K22

HA23_N

K23

GND

K24

HB00_P_CC

K25

HB00_N_CC

K26

GND

K27

HB06_P_CC

K28

HB06_N_CC

K29

GND

K30

HB10_P

K31

HB10_N

K32

GND

K33

HB14_P

K34

HB14_N

K35

GND

K36

HB17_P_CC

K37

HB17_N_CC

K38

GND

K39

VIO_B_M2C

K40

R36 4.99K

R36 4.99K

SDOSDO

J13F

SEAM-10X40PIN

J13F

SEAM-10X40PIN

PG_M2C

F1

GND

F2

GND

F3

HA00_P_CC

F4

HA00_N_CC

F5

GND

F6

HA04_P

F7

HA04_N

F8

GND

F9

HA08_P

F10

HA08_N

F11

GND

F12

HA12_P

F13

HA12_N

F14

GND

F15

HA15_P

F16

HA15_N

F17

GND

F18

HA19_P

F19

HA19_N

F20

GND

F21

HB02_P

F22

HB02_N

F23

GND

F24

HB04_P

F25

HB04_N

F26

GND

F27

HB08_P

F28

HB08_N

F29

GND

F30

HB12_P

F31

HB12_N

F32

GND

F33

HB16_P

F34

HB16_N

F35

GND

F36

HB19_P

F37

HB19_N

F38

GND

F39

VADJ

F40

J8

FPGA_GBT_REF_N

SMA

OPT

J8

FPGA_GBT_REF_N

SMA

OPT

JP1JP1

1

3

2

GNDGND

R58 1k

R58 1k

J13B

SEAM-10X40PIN

J13B

SEAM-10X40PIN

RES1

B1

GND

B2

GND

B3

DP9_M2C_P

B4

DP9_M2C_N

B5

GND

B6

GND

B7

DP8_M2C_P

B8

DP8_M2C_N

B9

GND

B10

GND

B11

DP7_M2C_P

B12

DP7_M2C_N

B13

GND

B14

GND

B15

DP6_M2C_P

B16

DP6_M2C_N

B17

GND

B18

GND

B19

GBTCLK1_M2C_P

B20

GBTCLK1_M2C_N

B21

GND

B22

GND

B23

DP9_C2M_P

B24

DP9_C2M_N

B25

GND

B26

GND

B27

DP8_C2M_P

B28

DP8_C2M_N

B29

GND

B30

GND

B31

DP7_C2M_P

B32

DP7_C2M_N

B33

GND

B34

GND

B35

DP6_C2M_P

B36

DP6_C2M_N

B37

GND

B38

GND

B39

RES0

B40

C37 47pF

C37 47pF

J13G

SEAM-10X40PIN

J13G

SEAM-10X40PIN

GND

G1

CLK0_C2M_P

G2

CLK0_C2M_N

G3

GND

G4

GND

G5

LA00_P_CC

G6

LA00_N_CC

G7

GND

G8

LA03_P

G9

LA03_N

G10

GND

G11

LA08_P

G12

LA08_N

G13

GND

G14

LA12_P

G15

LA12_N

G16

GND

G17

LA16_P

G18

LA16_N

G19

GND

G20

LA20_P

G21

LA20_N

G22

GND

G23

LA22_P

G24

LA22_N

G25

GND

G26

LA25_P

G27

LA25_N

G28

GND

G29

LA29_P

G30

LA29_N

G31

GND

G32

LA31_P

G33

LA31_N

G34

GND

G35

LA33_P

G36

LA33_N

G37

GND

G38

VADJ

G39

GND

G40

R57 0

R57 0

SDISDI

J13C

SEAM-10X40PIN

J13C

SEAM-10X40PIN

GND

C1

DP0_C2M_P

C2

DP0_C2M_N

C3

GND

C4

GND

C5

DP0_M2C_P

C6

DP0_M2C_N

C7

GND

C8

GND

C9

LA06_P

C10

LA06_N

C11

GND

C12

GND

C13

LA10_P

C14

LA10_N

C15

GND

C16

GND

C17

LA14_P

C18

LA14_N

C19

GND

C20

GND

C21

LA18_P_CC

C22

LA18_N_CC

C23

GND

C24

GND

C25

LA27_P

C26

LA27_N

C27

GND

C28

GND

C29

SCL

C30

SDA

C31

GND

C32

GND

C33

GA0

C34

12P0V

C35

GND

C36

12P0V

C37

GND

C38

3P3V

C39

GND

C40

R35 24.9

R35 24.9

R59 3.01k

R59 3.01k

R34 24.9

R34 24.9

CSCS

J13H

SEAM-10X40PIN

J13H

SEAM-10X40PIN

VREF_A_M2C

H1

PRSNT_M2C_N

H2

GND

H3

CLK0_M2C_P

H4

CLK0_M2C_N

H5

GND

H6

LA02_P

H7

LA02_N

H8

GND

H9

LA04_P

H10

LA04_N

H11

GND

H12

LA07_P

H13

LA07_N

H14

GND

H15

LA11_P

H16

LA11_N

H17

GND

H18

LA15_P

H19

LA15_N

H20

GND

H21

LA19_P

H22

LA19_N

H23

GND

H24

LA21_P

H25

LA21_N

H26

GND

H27

LA24_P

H28

LA24_N

H29

GND

H30

LA28_P

H31

LA28_N

H32

GND

H33

LA30_P

H34

LA30_N

H35

GND

H36

LA32_P

H37

LA32_N

H38

GND

H39

VADJ

H40

C41 0.1uF

C41 0.1uF

R38 4.99KR384.99K

J13D

SEAM-10X40PIN

J13D

SEAM-10X40PIN

PG_C2M

D1

GND

D2

GND

D3

GBTCLK0_M2C_P

D4

GBTCLK0_M2C_N

D5

GND

D6

GND

D7

LA01_P_CC

D8

LA01_N_CC

D9

GND

D10

LA05_P

D11

LA05_N

D12

GND

D13

LA09_P

D14

LA09_N

D15

GND

D16

LA13_P

D17

LA13_N

D18

GND

D19

LA17_P_CC

D20

LA17_N_CC

D21

GND

D22

LA23_P

D23

LA23_N

D24

GND

D25

LA26_P

D26

LA26_N

D27

GND

D28

TCK

D29

TDI

D30

TDO

D31

3P3VAUX

D32

TMS

D33

TRST_N

D34

GA1

D35

3P3V

D36

GND

D37

3P3V

D38

GND

D39

3P3V

D40

C38 47pF

C38 47pF

EEPROM

ARR

AY

U6

24LC32A

EEPROM

ARR

AY

U6

24LC32A

SDA

5

VCC

8

A0

1

A1

2

A2

3

GND

4

WP

7

SCL

6

J11

FPGA_SYS_REF_P

SMA

J11

FPGA_SYS_REF_P

SMA

Summary of Contents for DC1974 Series

Page 1: ...proper input networks for dif ferent input frequencies Design files for this circuit board are available at http www linear com demo DC1974 DC1974 VARIANTS ADC PART NUMBER RESOLUTION Bit MAXIMUM SAMP...

Page 2: ...ation with the host computer Follow the instructions in Appendix A for the Xilinx KC705 based system Verilog codemaybedownloadedfromtherespectiveADClanding page www linear com LTC2123 CHANNEL 1 SINGLE...

Page 3: ...or testing purposes only In the default configuration these SMAs are not used J9 and J10 FPGA_CLK This is an optional clock input port for the FPGA It is used for testing purposes only In the default...

Page 4: ...he DC1974 is single ended there is a transformer on the board that translates the single ended signal to a differential signal to drive the ADC ANALOG INPUT NETWORK In almost all cases off board filte...

Page 5: ...configure PScope Underthe Configure menu goto ADCConfiguration Check the Config Manually box and use the following configuration options shown in Figure 2 Manual Configuration settings Bits 14 Alignm...

Page 6: ...l to the device clock or device clock twice the sample rate n Off Default DEVCLK is equal to the sample rate n On DEVCLK is twice the sample rate Overflow Enables or disables the overflow bit in the o...

Page 7: ...riods to trigger the alert in subclass 1 Valid values are 1 to 8 Alert Mode Subclass 1 Only Enables or disables the alert mode n Disabled Default Alert mode is disabled n Enabled Alert mode is enabled...

Page 8: ...chnology will need to be configured as described in the Alternate FPGA Configuration section below 4 Apply power encode clock and analog input signals to the DC1974 board 5 VerifythatPScopesoftwareisi...

Page 9: ...CONNECT DC2159 TO PC 1 ASSEMBLE BOARDS 4 POWER UP DC1974 TURN ON CLOCK AND ANALOG INPUTS 3 CONFIGURE FPGA VIA JTAG IF NECESSARY THEN REMOVE USB CABLE 2 POWER UP KC705 dc1974 F05 Figure 5 KC705 Based D...

Page 10: ...16 1 L2 IND FERRITE BEAD 33 1206 MURATA BLM31PG330SN1L 17 0 L3 RES 1206 OPT 18 2 R1 R59 RES CHIP 3 01k 1 16W 1 0402 VISHAY CRCW04023K01FKED 19 1 R2 RES CHIP 10k 1 16W 1 0402 VISHAY CRCW040210K0FKED 20...

Page 11: ...TALL 40 0 MH1 MH2 STAND OFF ALUM M3 THREAD 5 0 HEX 4 40X1 KEYSTONE 24438 DO NOT INSTALL 41 2 STENCILS STENCILS TOP BOTTOM STENCIL DC1974A 3 DC1974A A Required Circuit Components 1 1 DC1974A GENERAL BO...

Page 12: ...NTACT LINEAR TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND SCHEMATIC SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS SCALE NONE www linear com 3...

Page 13: ...E25 GND E26 HB09_P E27 HB09_N E28 GND E29 HB13_P E30 HB13_N E31 GND E32 HB21_P E33 HB21_N E34 GND E35 HB20_P E36 HB20_N E37 GND E38 VADJ E39 GND E40 SCK SCK J13A SEAM 10X40PIN J13A SEAM 10X40PIN GND...

Page 14: ...RY INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE EXCEPT TO THE EXTENT OF THIS INDEMNITY NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT SPECIAL INCIDENTAL...

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