1
dc1974f
DEMO MANUAL DC1974
DESCRIPTION
LTC2124, LTC2123, LTC2122
14-Bit, 310Msps to 170Msps Dual
ADCs with JESD204B Outputs
Demonstration circuit 1974 supports the LTC
®
2124 14-bit
dual ADC family with JESD204B compliant CML outputs.
It was specially designed for applications that require
single-ended AC coupled inputs. The DC1974 supports
the
,
and
with sample rates
from 310Msps to 170Msps.
The specific ADC characteristics are listed in the DC1974
Variants section. The circuitry on the analog inputs is opti-
mized for analog input frequencies from 5MHz to 400MHz.
L
, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and PScope
is a trademark of Linear Technology Corporation. All other trademarks are the property of their
respective owners.
Refer to the data sheet for proper input networks for dif-
ferent input frequencies.
Design files for this circuit board are available at
http://www.linear.com/demo/DC1974
DC1974 VARIANTS
ADC PART NUMBER
RESOLUTION
(Bit)
MAXIMUM SAMPLE RATE
(Msps)
INPUT FREQUENCY
(MHz)
1974A-A
LTC2124
14
310
5 to 400
1974A-B
LTC2123
14
250
5 to 400
1974A-C
LTC2122
14
170
5 to 400
PARAMETER
CONDITION
MIN
TYP
MAX
UNIT
ADC Supply Voltage
This Supply Must Provide Up to 700mA
4
6
V
Analog Input Range
1.35
1.5
V
PP
Sampling Frequency (Device Clock Frequency)
Depending on ADC (1X CLK Mode)
10
310
MHz
Device Clock Level (Single-Ended at J3)
Minimum Logic Levels (DEV
CLK
+ Tied to GND)
0
V
Maximum Logic Levels (DEV
CLK
+ Tied to GND)
3.6
V
Device Clock Level (Differential Signal Across J3 and J4)
Minimum Logic Levels (DEV
CLK
+ Not Tied to GND,
1.2V Common Mode)
0.2
V
Digital Inputs (ADC_SYS_REF_N, ADC_SYS_REF_P,
SYNC_N, SYNC_P)
Differential Input Voltage
0.2
1.8
V
Common Mode Input Range
1.1
1.2
1.5
V
PERFORMANCE SUMMARY
Specifications are at T
A
= 25°C
DC1974 VARIANTS
