LTM4636
25
4636f
applicaTions inForMaTion
ambient, thus maximum junction temperature. Room
temperature power loss curves are provided in Figures 10
through 12. The printed circuit board is a 1.6mm thick six
layer board with two ounce copper for all layers and one
ounce copper for the two inner layers. The PCB dimensions
are 95mm
×
76mm.
Safety Considerations
The LTM4636 does not provide galvanic isolation from V
IN
to V
OUT
. There is no internal fuse. If required, a slow blow
fuse with a rating twice the maximum input current needs
to be provided to protect each unit from catastrophic failure.
The fuse or circuit breaker should be selected to limit the
current to the regulator during overvoltage in case of an
internal top MOSFET fault. If the internal top MOSFET
fails, then turning it off will not resolve the overvoltage,
thus the internal bottom MOSFET will turn on indefinitely
trying to protect the load. Under this fault condition, the
input voltage will source very large currents to ground
through the failed internal top MOSFET and enabled internal
bottom MOSFET. This can cause excessive heat and board
damage depending on how much power the input voltage
can deliver to this system. A fuse or circuit breaker can be
used as a secondary fault protector in this situation. The
LTM4636 has the enhanced over temperature protection
discussed earlier and schematic applications will be shown
at the end of the data sheet.
Layout Checklist/Example
The high integration of the LTM4636 makes the PCB
board layout very simple and easy. However, to optimize
its electrical and thermal performance, some layout
considerations are still necessary.
•
Use large PCB copper areas for high current paths,
including V
IN
, GND and V
OUT
. It helps to minimize the
PCB conduction loss and thermal stress.
•
Place high frequency ceramic input and output
capacitors next to the V
IN
, GND and V
OUT
pins to
minimize high frequency noise.
•
Place a dedicated power ground layer underneath the
unit.
•
To minimize the via conduction loss and reduce module
thermal stress, use multiple vias for interconnection
between top layer and other power layers.
•
Do not put vias directly on the pad, unless they are
capped or plated over.
•
Place test points on signal pins for testing.
•
Use a separated SGND ground copper area for
components connected to signal pins. Connect the
SGND to GND underneath the unit.
•
For parallel modules, tie the COMP and V
FB
pins together.
Use an internal layer to closely connect these pins
together.
•
R
SNUB
and C
SNUB
(2.2Ω and 2200pf) values to dampen
switch ringing.
Figure 19 gives a good example of the recommended layout.