LTM4636
19
4636f
applicaTions inForMaTion
Overtemperature Protection
The LTM4636 has an overtemperature enhanced protec-
tion features that can be used to detect overtemperature.
The overtemperature feature uses the TMON pin voltage
to monitor temperature. This pin varies from 0.994V at
25°C to 1.494 at 150°C, and will tripoff at ≥ 150°C. Tying
TMON to ground disable this feature.
RUNP and RUNC Enable
The RUNP pin is used to enable the 5V PV
CC
supply that
powers the power driver stage and enables the power
stage ~1ms later. The RUNC pin is used to enable the
control section that drives the power stage. The RUNP
needs to be enabled first, and then RUNC. RUNP has a
0.85V threshold and can be connected to the input volt-
age and RUNC has a 1.35V threshold and a 10k resistor
to ground. See the Block Diagram for details. A 0.1µF
capacitor from the RUNC pin to ground is used to set the
delay for RUNC enable.
INTV
CC
and PV
CC
Regulators
The LTM4636 has an internal low dropout regulator from
V
IN
called INTV
CC
. This regulator output has a 4.7μF
ceramic capacitor internal. This regulator powers the
control section. The PV
CC
5V regulator supplies power
to the power MOSFET driver stage. An additional 50mA
can be used from this 5V PV
CC
supply for other needs.
The input supply source resistance needs to be very low
in order to minimize IR drops when operating from a 5V
input source. Depending on the output voltage and current,
the input supply can source large current,and PV
CC
5V
regulator needs a minimum 4.70V supply. Additional
input capacitance maybe needed for 5V inputs to limit
the input droop.
Stability Compensation
The LTM4636 has already been internally compensated
when COMPB is tied to COMPA for all output voltages.
Table 5 is provided for most application requirements.
For specific optimized requirements, disconnect COMPB
from COMPA, and use LTpowerCAD to perform specific
control loop optimization. Then select the desired external
compensation and output capacitance for the desired
optimized response.
SW Pins
The SW pins are generally for testing purposes by moni-
toring these pins. These pins can also be used to dampen
out switch node ringing caused by LC parasitic in the
switched current paths. Usually a series R-C combina-
tion is used called a snubber circuit. The resistor will
dampen the resonance and the capacitor is chosen to
only affect the high frequency ringing across the resistor.
If the stray inductance or capacitance can be measured or
approximated then a somewhat analytical technique can
be used to select the snubber values. The inductance is
usually easier to predict. It combines the power path board
inductance in combination with the MOSFET interconnect
bond wire inductance.
First the SW pin can be monitored with a wide bandwidth
scope with a high frequency scope probe. The ring fre-
quency can be measured for its value. The impedance Z
can be calculated:
Z(L) = 2πfL,
where f is the resonant frequency of the ring, and L is the
total parasitic inductance in the switch path. If a resistor
is selected that is equal to Z, then the ringing should be
dampened. The snubber capacitor value is chosen so that
its impedance is equal to the resistor at the ring frequency.
Calculated by: Z(C) = 1/(2πfC). These values are a good
place to start with. Modification to these components
should be made to attenuate the ringing with the least
amount of power loss. A recommended value of 2.2Ω in
series with 2200pF to ground should work for most ap-
plications. See Figure 19 for guideline. The 2.2Ω resistor
should be an 0805 size.
Thermal Considerations and Output Current Derating
The thermal resistances reported in the Pin Configuration
section of the data sheet are consistent with those param-
eters defined by JESD51-12 and are intended for use with
finite element analysis (FEA) software modeling tools that
leverage the outcome of thermal modeling, simulation,
and correlation to hardware evaluation performed on a
µModule package mounted to a hardware test board.
The motivation for providing these thermal coefficients
in found in JESD51-12 (“Guidelines for Reporting and
Using Electronic Package Thermal Information”).