3. TECHNICAL BRIEF
- 17 -
(1) Receiver Part
A. LNA and Quadrature Demodulator
Four separate LNAs are integrated in the SKY74400 to address different bands of operation. These LNAs
have separate singleended 50 inputs. The LNA gain is switchable between high and low settings using the
three-wire bus. The LNA outputs feed into a quadrature demodulator that downconverts the RF signals
directly to baseband. The baseband I and Q paths consist of cascaded amplifiers and low pass filter
sections. The baseband section provides eight programmable bandwidth settings ranging between 90 kHz
and 160 kHz to allow for added flexibility when interfacing to any mixed signal baseband device.
No external capacitors are required for baseband filtering. The filter chain consists of two fixed real poles,
two fixed conjugate pole pairs, and one programmable conjugate pole pair. The result is a flat passband
with minimal group delay distortion at any bandwidth setting.
B. DC Offset Correction
Five DC offset correction loops ensure that DC offsets generated in the SKY74400 do not overload the
baseband chain at any point. After correction, the corrected voltages are held digitally for the duration of the
receive slot(s). The positive edge of the RXENA signal starts the digital DC offset correction. Since the
correction is digital, a system clock is required.
To generate the clock, the reference frequency is divided down internally. A special, fast DC offset
correction is carried out every time the receiver gain is programmed while RXENA is high. This ensures that
a DC offset correction is complete in the time available, even if the gain is changed between slots in
multislot mode.
C. AM Suppression and IP2 Calibration
For direct conversion GSM applications, it is imperative to have extremely low second-order distortion.
Mathematically, secondorder distortion of a constant tone generates a DC term proportional to the square of
the amplitude. In general, a strong interfering Amplitude Modulated (AM) signal is, therefore, demodulated
by second-order distortion, which generates an Acinterfering baseband signal. The SKY74400 can
effectively handle such AM-modulated interferers. A commonly used measure for receiver second-order
distortion is the second-order intercept point, IP2. For example, to ensure that the unwanted baseband
signals are 9 dB below the wanted signal required under the AM suppression test for type approval (see
3GPP TS 51.010-1), an input IP2 of 43 dBm is required. The SKY74400 RF transceiver includes a circuit
that minimizes second-order distortion. This IP2 calibration circuit effectively compensates for any second-
order distortion in the receive chain that would otherwise generate unwanted baseband signals in the
presence of strong interfering signals. When calibrated correctly, the SKY74400 IP2 meets the GSM AM
suppression test requirements in all bands with good margin.
A one-time factory calibration procedure produces a set of I/Q compensation coefficients that are
programmed in the device to minimize the DC voltage shift resulting from the second-order distortion. The
IP2 performance is optimized when the DC due to the interfering signal is minimized. The determined
coefficients are transmitted to the serial interface, stored in nonvolatile memory, and programmed to the
SKY74400 upon each power-up as part of device initialization. The optimization process is performed
internal to the SKY74400.
Summary of Contents for M6100
Page 1: ...Date February 2006 Issue 1 0 Service Manual Model M6100 Service Manual M6100 ...
Page 3: ... 4 ...
Page 15: ...3 TECHNICAL BRIEF 16 Figure 3 1 SKY74400 FUNCTIONAL BLOCK DIAGRAM ...
Page 40: ...3 TECHNICAL BRIEF 41 3 7 CAMERA IC AIT813 U701 Figure 3 18 AIT813 APPLICATION BLOCKDIAGRAM ...
Page 42: ...3 TECHNICAL BRIEF 43 3 8 MIDI IC YMU787 U708 Figure 3 20 YMU787 BLOCKDIAGRAM ...
Page 63: ...4 2 TX Trouble 4 TROUBLE SHOOTING 64 SKY74400 FEM 13Mhz OSCILLATOR TEST POINT Figure 4 2 ...
Page 98: ...4 TROUBLE SHOOTING 99 4 16 Camera and Flash Trouble Camera Module CN802 U704 U705 Figure 4 17 ...
Page 109: ... 110 ...
Page 119: ... 120 8 PCB LAYOUT ...
Page 120: ... 121 8 PCB LAYOUT ...
Page 121: ... 122 8 PCB LAYOUT ...
Page 122: ... 123 8 PCB LAYOUT ...
Page 123: ... 124 ...
Page 131: ...10 STAND ALONE TEST 132 Figure 10 2 HW test setting Figure 10 3 Ramping profile ...
Page 137: ... 138 ...
Page 159: ...Note ...
Page 160: ...Note ...