3. TECHNICAL BRIEF
- 44 -
CPU INTERFACE
CPU interface is an 8-bit parallel.
4 control signal(/wr,/rd,/cs,A0 pin), 8 data bit(D0 to D7), and 1 interrupt pin(/IRQ), totaling 13 pins are
connected to the external CPU. This block controls the writing and reading of data by the input polarity of
control signal
INTERFACE REGISTER
This registeris able to access directly ffrom the external CPU. There are 2 bytes spaces. The Intermediate
register can be accessed through the interface register.
INTERMEDIATE REGISTER
This register is accessed through the Interface register.
It is composed to access a latter control register and ROM/SRAM through Intermediate register.
This register is called “Intermediate register” since this exists in the middle of the interface register and the
Control register. In the Intermediate register, there are some registers to control various functions.
Close to SPEAKER
0
C738
0.022u
C734
3.3K
R730
VBAT
R725
FB705
68K
R726
33K
C752
1u
SPOUT2R
SPVDDL
A6
J6
SPVDDR
A7
SPVSSL
SPVSSR1
H7
J7
SPVSSR2
E8
TXOUT
VREF
F7
_CS
H3
_IRQ
D4
H4
_RD
_RST
B4
_WR
J2
H1
B3
IOVDD2
C2
LDE1_GPIO4
LED0
C3
LED2_GPIO5
B1
D3
LRCK
B2
MTR
NC1
A1
A8
NC2
J1
NC3
H5
PLLC
RXIN
C6
SDI
D1
B7
SPOUT1L
SPOUT1R
J8
B8
SPOUT2L
H8
EQ1R
A4
EQ2L
EQ2R
G6
EQ3L
A5
H6
EQ3R
G7
EXC
B6
EXTIN
EXTOUT
D7
D6
GPIO0
C5
GPIO1
GPIO2
C1
GPIO3
C4
F6
HPC
C8
HPOUTL
C7
HPOUTR
HPVSS
D8
IOVDD1
G5
H2
D0
D1
G3
G2
D2
D3
F3
G1
D4
D5
F2
E3
D6
D7
E2
DVDD1
J4
DVDD2
A2
F1
DVDD3
J3
DVSS1
DVSS2
A3
DVSS3
E1
EQ1L
B5
J5
YMU787
G4
A0
AVDD
G8
F8
AVSS
E6
BBL
BBR
E7
D2
BLCK
CLKI
0
R733
U708
4.7u
C755
C751
0.1u
C733
120p
0.1u
C753
0
R731
2V8_MV
1u
C758
0.1u
C750
0.1u
C762
C754
0.1u
1000p
C735
NA
R732
0
C749
C737
0.022u
1u
C760
C757
0.1u
1u
C761
C756
4.7u
C743
47p
NA
C742
33K
R728
1V8_MV
C759
1u
TP702
2V8_VEXT
NA
R734
C744
47p
0
C748
68K
R724
MIDI_HP_L
MIDI_HP_R
SPKPM
DATA10
DATA11
DATA12
DATA13
DATA14
DATA15
SPK_N
13MHz
SPK_P
ADD00
_MIDI_CS
_RD
_MIDI_RST
_MIDI_IRQ
_WR
DATA08
DATA09
Figure 3-21. YMU787 CIRCUIT DIAGRAM
Summary of Contents for M6100
Page 1: ...Date February 2006 Issue 1 0 Service Manual Model M6100 Service Manual M6100 ...
Page 3: ... 4 ...
Page 15: ...3 TECHNICAL BRIEF 16 Figure 3 1 SKY74400 FUNCTIONAL BLOCK DIAGRAM ...
Page 40: ...3 TECHNICAL BRIEF 41 3 7 CAMERA IC AIT813 U701 Figure 3 18 AIT813 APPLICATION BLOCKDIAGRAM ...
Page 42: ...3 TECHNICAL BRIEF 43 3 8 MIDI IC YMU787 U708 Figure 3 20 YMU787 BLOCKDIAGRAM ...
Page 63: ...4 2 TX Trouble 4 TROUBLE SHOOTING 64 SKY74400 FEM 13Mhz OSCILLATOR TEST POINT Figure 4 2 ...
Page 98: ...4 TROUBLE SHOOTING 99 4 16 Camera and Flash Trouble Camera Module CN802 U704 U705 Figure 4 17 ...
Page 109: ... 110 ...
Page 119: ... 120 8 PCB LAYOUT ...
Page 120: ... 121 8 PCB LAYOUT ...
Page 121: ... 122 8 PCB LAYOUT ...
Page 122: ... 123 8 PCB LAYOUT ...
Page 123: ... 124 ...
Page 131: ...10 STAND ALONE TEST 132 Figure 10 2 HW test setting Figure 10 3 Ramping profile ...
Page 137: ... 138 ...
Page 159: ...Note ...
Page 160: ...Note ...