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34
I/O
Description
Remarks
OUT MPEG DATA output
-
Digital GND (0V)
For Logic cell
-
DV
DD3
, Digital (3.3V)
For Logic cell
OUT MPEG DATA output
OUT MPEG DATA output
OUT MPEG DATA output
OUT MPEG DATA output
OUT
MPEG DATA Reliability Flag (Data Error= "L")
OUT MPEG output Sector Synchronizing signal (Sector top= "L" )
OUT MPEG DATA Active Flag (Active mode= "L")
OUT MPEG DATA Transfer Clock
-
Digital GND (0V)
For Logic cell
IN
MPEG Data demand Flag (demand= "L" )
TTL level
IN
H/W Reset input (Reset= "L" )
-
Digital DV
DD3
(3.3V)
For Logic cell
OUT Operating Condition Monitor Data (SDCK Synchronizing output)
PWM Combination
OUT Operating Condition Monitor Synchronizing signal (Data Top Bit="L")
PWM Combination
OUT Genearl purpose PWM output
4mA, 5V-I/F
-
Digital GND (0V)
For Logic cell
Pin No.
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Pin Name
SD4
DVSS
DVDD3
SD3
SD2
SD1
SD0
SERR
SBGN
SENB
SDCK
DVSS
SREQ
RSTN
DVDD3
STDA
STCK
UPWM
DVSS
*
Digital IN/OUT terminal as not described in remarks is CMOS Level (5V).