![background image](http://html.mh-extra.com/html/lg/drd-820b/drd-820b_manual_211110027.webp)
32
I/O
Description
IN
Signal management reference clock input
-
Digital VDD3 (3.3V)
IN
Servo reference clock input (oscillating circuit input)
OUT
Servo reference clock output (oscillating circuit input)
-
Digital GND (0V)
-
Digital DV
DD3
(3.3V)
-
Not use.
IN
MPU write signal
IN
MPU read signal
IN
MPU chip select
I/O
MPU Data BUS
I/O
MPU Data BUS
I/O
MPU Data BUS
I/O
MPU Data BUS
I/O
MPU Data BUS
I/O
MPU Data BUS
I/O
MPU Data BUS
I/O
MPU Data BUS
-
Digital GND (0V)
-
Digital DV
DD5
(5V)
OUT
MPU interrupt signal ("L" is in the interrupt mode)
IN
MPU Address
IN
MPU Address
I/O
Read CH clock I/O port
-
Not use.
-
-
-
-
-
-
-
IN
For production adjustment
OUT
PLL phase error signal output (-)
OUT
PLL phase error signal output (+)
OUT
Output as a result of RLL detection
IN
(-) Input of AMD for PLL loop filter
OUT
AMP output for PLL loop filter
OUT
VCO Filter terminal
OUT
Reference voltage output of Enhanced comparator
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Pin Name
DPCKI
DVDD3
SVCKI
SVCKO
DVSS
DVDD3
N.C.
HDWT
HDRD
HCEN
HD0
HD1
HD2
HD3
HD4
HD5
HD6
HD7
DVSS
DVDD5
HINT
HA0
HA1
PLCK
ED0
ED1
ED2
ED3
ED4
ED5
ED6
ED7
TEST
PDON
PDOP
RLLD
LPFN
LPFO
VCOF
SLCO
IC401 (TC90A41AF)
Pin Description
Remarks
0.5~3.3Vpp
Enhanced feedback resistor
Logic cell
3.3V-I/F
Enhanced feedback resistor
For Logic cell
For Logic cell
open
TTL level
TTL level
TTL level
TTL level
TTL level
TTL level
TTL level
TTL level
TTL level
TTL level
TTL level
For I/O cell
For I/O cell
OPEN DRAIN
TTL level
TTL level
OPEN
Set to "L"