Lexicon
6-5
Read Only
Digital Audio Receiver Status
ZD Bus Bits
7:4
3
2
1
0
Function
N/A
Auto
FS96
ERF
Validity
Auto:
= 1: AC-3 or MPEG Detect
= 0: No Detection
FS96:
= 1: Fs >= 88.2kHz
= 0: Fs <= 54 kHz
ERF: This bit is the logical OR of PLL, Parity, Biphase, and Frame Length status.
= 1: PLL unlocked, Biphase, Parity, or Frame Length error
= 0: No error
Validity: Direct status of validity bit.
U23 is an eight bit wide read buffer that provides status of the footswitch, rotary encoder, and front panel
push button switches to the Z80 processor via the internal data bus. STAT_RD/ is an address-decoded chip
select for this read buffer.
Address: 0x4C00
Function: Switch Status read
Read Only
Switch Status
ZD Bus bits
7
6
5
4
3:0
Signal
Foot_Bypass/
Foot_Tap/
Switch_Row1/
Switch_Row0/
ENC_3:0
Foot_Bypass/:
= 1: Foot_Bypass/ switch is not pressed
= 0: Foot_Bypass/ switch is pressed
Foot_Tap:
= 1: Foot_Tap/ switch is not pressed
= 0: Foot_Tap/ switch is pressed
Switch_Row1/:
This is the OR of the Bypass, Edit, and Tap/Cancel front panel switches. The actual switch status is column
scan dependent.
= 1: One of the above three switches is pressed
= 0: None of the above switches have been pressed.
Switch_Row0/:
This is the OR of the Store, Compressor, and Load front panel switches. The actual switch status is column
scan dependent.
= 1: One of the above three switches is pressed
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