Lexicon 200, Service Manual

Page: 40 / 90

MPX 200 Service Manual
6-4
S/PDIF Input
The S/PDIF input is brought in via one half of J5. The signal is terminated into 75
Ω
by R129, AC coupled by
C103, and amplified by U18 (74HCU04). Current limiting resistor R127 and clamping diode D6 provide
input protection. R126 and R128 force one section of U18 into a semi-linear mode of operation creating a
gain stage that amplifies the low-level signal at the input to a CMOS logic level. The second section of U18
provides additional buffering of this signal. R122 is a provision added to the design to bypass this gain and
buffer stage for higher level signals, but this provision has not been implemented. C108 and R146 are
provisions for either AC or DC coupling the ground signals of the S/PDIF connector to chassis ground via
mechanical contact with the chassis. Currently, the ground signals for the S/PDIF input and output are DC
coupled via R146, with C108 left unpopulated.
S/PDIF Output
The S/PDIF OUT is generated by the Lexichip3 and buffered by two gate sections of U18. These two gates
of U18 are connected in parallel to increase drive capability. The resistor combination of R123-R125 forms
a voltage divider that attenuates the buffered signal to 500mVp-p. D5 clamps this voltage to +/- 0.7V. The
resultant signal is AC coupled by C100 and C101 to the output section of J5. C102 prevents high frequency
radiation from getting out onto the cable connected to S/PDIF out.
AK4112 Digital Audio Receiver
The digital audio receiver AK4112 (U13), which delivers a serial stream in I2S format to the Lexichip3,
demodulates the amplified signal from the S/PDIF input circuitry. The signals V/TX, FS96, AUTO, and ERF
allow software to determine the Validity, sample rate, PCM detection status, and error status detected by
U13. The chip is hardwired to 24 bit I2S format, and it may be set as a timing master or slave by toggling
the DIF1 signal (SP_MASTER). This is accomplished by programming the Lexichip3 PIOB_4 pin. When this
signal is low, the receiver is in master mode; when 0, the receiver is set to slave mode. The MPX200 is
always operated in slave mode. The receiver is hardwired to work in parallel mode, with the master clock
source set to be the internal PLL. Master clock output MCK01 is hardwired to provide 256fs locked to the
recovered clock from the input data stream. During a reset cycle, provided by the signal RESET/ tied to the
PDN pin, All internal analog and digital circuits become inactive, along with all clocks. All internal control
registers are held in reset also.
C88 and C89 provide power supply de-coupling for the Input Buffer supply pin. C85 and C86 de-couple the
digital supply to the chip. C91 and C92 de-couple the analog supply to the chip. R110 provides a bias
current for the analog circuitry internal to the AK4112.
R108 and R112 are provisions for alternative DC coupling of the recovered master clock from the AK4112
and also from it’s buffered equivalent as provided by U15. This was done in order to address potential
radiated emissions; if the product was found to be radiating beyond acceptable limits, R108 and R112 may
be replaced by ferrite beads. It was found to not be necessary, so R108 and R112 are 0 ohm resistors.
This device is run off of 3.3 Volts DC. All the I/O on this device is 5 Volt tolerant.
U15 buffers the 256fs master clock and the Serial data to the Lexichip3. This buffer provides level
translation between the 3.3V logic level of the Receiver to the 5V logic level of the Lexichip3. Series
resistors R109 and R111 provide protection from signal over-and under-shoot, which can cause the unit to
radiate high frequencies.
LRCLK and BICK provide 44.1 kHz frame clock (LEX_FS/) and 64fs (LEX_64FS/) when the receiver is in
master mode. In slave mode, these pins become inputs and Lexichip3 provides the clocks.
U15 is a 4 bit wide read buffer that provides status of the AK4112 to the Z80 processor via the internal data
bus. SP_STAT/ is an address-decoded chip select for this buffer.
Address: 0x4C01
Function: Digital Audio Receiver Status